From: Robin Dapp <rdapp@oss.qualcomm.com>
Date: Fri, 23 Jan 2026 08:25:56 +0000 (+0100)
Subject: RISC-V: testsuite: Add vector requirement to test.
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=38927ecc9dbcae94565b58c1de51b5168709cc9e;p=thirdparty%2Fgcc.git

RISC-V: testsuite: Add vector requirement to test.

This adds the missing vector requirement to rvv/base/pr122869.c

Signed-off-by: Robin Dapp <rdapp@oss.qualcomm.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr122869.c: Add
	vector requirement.
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c
index e00ac04bebb..6f9be80841c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c
@@ -1,5 +1,7 @@
-/* { dg-do run } */
+/* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-O0 -std=gnu99" } */
+/* { dg-require-effective-target riscv_v_ok } */
+
 /* We used to generate a separate riscv_read_vl () after the FoF load.
    In case of -O0 (or otherwise) it could happen that "g" wouldn't
    get a hard reg and we'd need to store it, clobbering VL.