From: Djordje Todorovic Date: Thu, 8 Jan 2026 13:41:36 +0000 (+0000) Subject: target/riscv: Add MIPS P8700 CPU X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=38e63ea61a4b84349f98550495038b20e4db099e;p=thirdparty%2Fqemu.git target/riscv: Add MIPS P8700 CPU Introduce P8700 CPU by MIPS. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260108134128.2218102-3-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 75f4e43408..30dcdcfaae 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -56,6 +56,7 @@ #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") +#define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2222228d5..3562cbec32 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3303,6 +3303,22 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV48, ), + /* https://mips.com/products/hardware/p8700/ */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max = MXL_RV64, + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, + .priv_spec = PRIV_VERSION_1_12_0, + .cfg.max_satp_mode = VM_1_10_SV48, + .cfg.ext_zifencei = true, + .cfg.ext_zicsr = true, + .cfg.mmu = true, + .cfg.pmp = true, + .cfg.ext_zba = true, + .cfg.ext_zbb = true, + .cfg.marchid = 0x8000000000000201, + .cfg.mvendorid = MIPS_VENDOR_ID, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV57, diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h index 96b6b9c2cb..f1ffc66542 100644 --- a/target/riscv/cpu_vendorid.h +++ b/target/riscv/cpu_vendorid.h @@ -2,6 +2,7 @@ #define TARGET_RISCV_CPU_VENDORID_H #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x127 #define VEYRON_V1_MARCHID 0x8000000000010000 #define VEYRON_V1_MIMPID 0x111