From: Mukul Joshi Date: Mon, 15 Sep 2025 14:48:04 +0000 (-0400) Subject: drm/amdgpu: Update TCP Control register on GFX 12.1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3af6302d8c2ee37b9a791222947052ee2dfdea5b;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: Update TCP Control register on GFX 12.1 Update TCP CNTL register to disable some features not supported on GFX 12.1. Signed-off-by: Mukul Joshi Reviewed-by: Alex Sierra Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 7d4b241fc3a4..59bbb9a5d298 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2668,6 +2668,17 @@ static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); } +static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); + data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); +} + static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { int i; @@ -2677,6 +2688,7 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) gfx_v12_1_xcc_enable_atomics(adev, i); gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i); gfx_v12_1_xcc_disable_early_write_ack(adev, i); + gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); } }