From: Carl Love <cel@linux.ibm.com>
Date: Wed, 23 Oct 2024 23:25:23 +0000 (-0500)
Subject: PowerPC, dcbf instruction
X-Git-Tag: VALGRIND_3_24_0~26
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3b1a12795cc5cbb57dbf0219375229094c86122e;p=thirdparty%2Fvalgrind.git

PowerPC, dcbf instruction

ISA 2.7 and ISA 3.0 "accepts" L = 0 to 3, ISA 3.1 "accepts: L = 0 to 7.
Removed the L field check so valgrind will match the real hardware.  For
the purposes of Valgrind the dcbf instruction is a NOP anyway so it will
not change the behavior of Valgrind.
---

diff --git a/NEWS b/NEWS
index b375fa268..acefe2418 100644
--- a/NEWS
+++ b/NEWS
@@ -81,6 +81,8 @@ are not entered into bugzilla tend to get forgotten about or ignored.
         FUSE_COMPATIBLE_MAY_BLOCK
 493970  s390x: Store/restore FPC upon helper call causes slowdown
 494252  s390x: incorrect disassembly for LOCHI and friends
+495278  PowerPC instruction dcbf should allow the L field values of 4, 6 on
+        ISA 3.0 and earlier, just ignore the value
 n-i-bz  Improve messages for sigaltstack errors, use specific
         stack_t member names
 
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index d05cce394..94930aa1c 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -12145,7 +12145,10 @@ static Bool dis_cache_manage ( UInt prefix, UInt theInstr,
    UChar opc1    = ifieldOPC(theInstr);
    UChar b21to25 = ifieldRegDS(theInstr);
    /* The L-field is 2 bits in ISA 3.0 and earlier and 3 bits in ISA 3.1 */
-   UChar flag_L  = IFIELD(theInstr, 21, (allow_isa_3_1 ? 3 : 2));
+   /* Relaxed the test to mach actual hardware, accept all L values from 0 to 7.
+      The hardware ignores the L value if not supported.      10/23/2024
+      UChar flag_L  = IFIELD(theInstr, 21, (allow_isa_3_1 ? 3 : 2));  */
+
    UChar rA_addr = ifieldRegA(theInstr);
    UChar rB_addr = ifieldRegB(theInstr);
    UInt  opc2    = ifieldOPClo10(theInstr);
@@ -12203,15 +12206,19 @@ static Bool dis_cache_manage ( UInt prefix, UInt theInstr,
          dcbf ra, rb, 0          dcbf
          dcbf ra, rb, 1          dcbf local
          dcbf ra, rb, 3          dcbf local primary
-         dcbf ra, rb, 4          dcbf block fjush to persistent storage    isa 3.1
-         dcbf ra, rb, 6          dcbf block store to persistent storage    isa 3.1
- */
-               if (!((flag_L == 0 || flag_L == 1 || flag_L == 3)
-               || ((flag_L == 4 || flag_L == 6) && allow_isa_3_1 == True)))
+         dcbf ra, rb, 4          dcbf block fjush to persistent storage isa 3.1
+         dcbf ra, rb, 6          dcbf block store to persistent storage isa 3.1
+         Relaxed requirement to allow all L values from 0 to 7 to match the
+         operation of the real hardware.  The real hardware accepts the
+         unsupported L values.      10/23/2024
+
+         if (!((flag_L == 0 || flag_L == 1 || flag_L == 3)
+           || ((flag_L == 4 || flag_L == 6) && allow_isa_3_1 == True)))
          {
             vex_printf("dis_cache_manage(ppc)(dcbf,flag_L)\n");
             return False;
          }
+      */
       /* nop as far as vex is concerned */
       break;