From: Dave Jiang Date: Mon, 17 Mar 2025 16:22:59 +0000 (-0700) Subject: Merge branch 'for-6.15/features' into cxl-for-next X-Git-Tag: v6.15-rc1~45^2~1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3b5d43245f0a56390baaa670e1b6d898772266b3;p=thirdparty%2Fkernel%2Fstable.git Merge branch 'for-6.15/features' into cxl-for-next Add CXL Features support. Setup code for enabling in kernel usage of CXL Features. Expecting EDAC/RAS to utilize CXL Features in kernel for things such as memory sparing. Also prepartion for enabling of CXL FWCTL support to issue allowed Features from user space. --- 3b5d43245f0a56390baaa670e1b6d898772266b3 diff --cc drivers/cxl/core/Makefile index c390f7edc3775,b0bfbd9eac9be..086df97a0fcfb --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@@ -14,8 -14,6 +14,9 @@@ cxl_core-y += pci. cxl_core-y += hdm.o cxl_core-y += pmu.o cxl_core-y += cdat.o +cxl_core-y += ras.o +cxl_core-y += acpi.o cxl_core-$(CONFIG_TRACING) += trace.o cxl_core-$(CONFIG_CXL_REGION) += region.o +cxl_core-$(CONFIG_CXL_MCE) += mce.o + cxl_core-$(CONFIG_CXL_FEATURES) += features.o diff --cc drivers/cxl/core/core.h index e35f6e08ddb5b,17e99a25c29a5..15699299dc11d --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@@ -115,10 -117,15 +117,21 @@@ bool cxl_need_node_perf_attrs_update(in int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); +int cxl_ras_init(void); +void cxl_ras_exit(void); +int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port); +int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, + int nid, resource_size_t *size); + + #ifdef CONFIG_CXL_FEATURES + size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, + enum cxl_get_feat_selection selection, + void *feat_out, size_t feat_out_size, u16 offset, + u16 *return_code); + int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, + u8 feat_version, const void *feat_data, + size_t feat_data_size, u32 feat_flag, u16 offset, + u16 *return_code); + #endif + #endif /* __CXL_CORE_H__ */ diff --cc drivers/cxl/core/mbox.c index 7450c4df522e2,78c5346e3e891..d72764056ce62 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@@ -1469,14 -1477,11 +1498,15 @@@ struct cxl_memdev_state *cxl_memdev_sta mutex_init(&mds->event.log_lock); mds->cxlds.dev = dev; mds->cxlds.reg_map.host = dev; + mds->cxlds.cxl_mbox.host = dev; mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE; mds->cxlds.type = CXL_DEVTYPE_CLASSMEM; - mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID; - mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID; + + rc = devm_cxl_register_mce_notifier(dev, &mds->mce_notifier); + if (rc == -EOPNOTSUPP) + dev_warn(dev, "CXL MCE unsupported\n"); + else if (rc) + return ERR_PTR(rc); return mds; } diff --cc drivers/cxl/core/memdev.c index f119309d0c9be,2e2e035abdaae..a16a5886d40a7 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@@ -580,9 -564,12 +580,11 @@@ EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CX void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds) { + struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; + - down_write(&cxl_memdev_rwsem); + guard(rwsem_write)(&cxl_memdev_rwsem); - bitmap_or(mds->exclusive_cmds, mds->exclusive_cmds, cmds, - CXL_MEM_COMMAND_ID_MAX); + bitmap_or(cxl_mbox->exclusive_cmds, cxl_mbox->exclusive_cmds, + cmds, CXL_MEM_COMMAND_ID_MAX); - up_write(&cxl_memdev_rwsem); } EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, "CXL"); @@@ -594,9 -581,12 +596,11 @@@ void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds) { + struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; + - down_write(&cxl_memdev_rwsem); + guard(rwsem_write)(&cxl_memdev_rwsem); - bitmap_andnot(mds->exclusive_cmds, mds->exclusive_cmds, cmds, - CXL_MEM_COMMAND_ID_MAX); + bitmap_andnot(cxl_mbox->exclusive_cmds, cxl_mbox->exclusive_cmds, + cmds, CXL_MEM_COMMAND_ID_MAX); - up_write(&cxl_memdev_rwsem); } EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, "CXL"); diff --cc drivers/cxl/cxlmem.h index db565d4a9e3c4,dd2b7060d501c..3ec6b906371b6 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@@ -468,20 -408,11 +433,23 @@@ struct cxl_dev_state u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; + #ifdef CONFIG_CXL_FEATURES + struct cxl_features_state *cxlfs; + #endif }; +static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds) +{ + /* + * Static PMEM may be at partition index 0 when there is no static RAM + * capacity. + */ + for (int i = 0; i < cxlds->nr_partitions; i++) + if (cxlds->part[i].mode == CXL_PARTMODE_PMEM) + return resource_size(&cxlds->part[i].res); + return 0; +} + static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) { return dev_get_drvdata(cxl_mbox->host); diff --cc tools/testing/cxl/Kbuild index a7ec67d4a0f2b,0a6572ab6f372..387f3df8b9885 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@@ -61,11 -61,9 +61,12 @@@ cxl_core-y += $(CXL_CORE_SRC)/pci. cxl_core-y += $(CXL_CORE_SRC)/hdm.o cxl_core-y += $(CXL_CORE_SRC)/pmu.o cxl_core-y += $(CXL_CORE_SRC)/cdat.o +cxl_core-y += $(CXL_CORE_SRC)/ras.o +cxl_core-y += $(CXL_CORE_SRC)/acpi.o cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o +cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o + cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o cxl_core-y += config_check.o cxl_core-y += cxl_core_test.o cxl_core-y += cxl_core_exports.o