From: Uros Bizjak <ubizjak@gmail.com>
Date: Tue, 14 Jan 2014 19:28:36 +0000 (+0100)
Subject: Revert:
X-Git-Tag: releases/gcc-4.7.4~319
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3ba4ee8278d0804b4bd789ff1f11c74d718bdfea;p=thirdparty%2Fgcc.git

Revert:

	2014-01-08  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.c (ix86_data_alignment): Calculate max_align
	from prefetch_block tune setting.

From-SVN: r206607
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 878eb66f0eec..edcbb91e4002 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-01-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	Revert:
+	2014-01-08  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_data_alignment): Calculate max_align
+	from prefetch_block tune setting.
+
 2014-01-10  Richard Earnshaw  <rearnsha@arm.com>
 
 	PR rtl-optimization/54300
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 63622abf78b3..cc53a6262d15 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -24266,16 +24266,8 @@ ix86_constant_alignment (tree exp, int align)
 int
 ix86_data_alignment (tree type, int align)
 {
-  /* A data structure, equal or greater than the size of a cache line
-     (64 bytes in the Pentium 4 and other recent Intel processors, including
-     processors based on Intel Core microarchitecture) should be aligned
-     so that its base address is a multiple of a cache line size.  */
-
   int max_align
-    = MIN ((unsigned) ix86_cost->prefetch_block * 8, MAX_OFILE_ALIGNMENT);
-
-  if (max_align < BITS_PER_WORD)
-    max_align = BITS_PER_WORD;
+    = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
 
   if (AGGREGATE_TYPE_P (type)
       && TYPE_SIZE (type)