From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 28 Oct 2025 12:17:38 +0000 (+0100)
Subject: airoha: an7581: correctly attach the USB2 PHY for 3rd PCIe line
X-Git-Tag: v25.12.0-rc1~741
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3ba92e0e3268c07859859968368602d2dc758148;p=thirdparty%2Fopenwrt.git

airoha: an7581: correctly attach the USB2 PHY for 3rd PCIe line

The 3rd PCIe line use the USB2 serdes for PCIe operation. Correctly set
it to the DT node so that the mode can be correctly set in the PHY
driver.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---

diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi
index 367779e544f..32bc6b5df7d 100644
--- a/target/linux/airoha/dts/an7581.dtsi
+++ b/target/linux/airoha/dts/an7581.dtsi
@@ -780,7 +780,7 @@
 			clocks = <&scuclk EN7523_CLK_PCIE>;
 			clock-names = "sys-ck";
 
-			phys = <&pciephy>;
+			phys = <&usb1_phy PHY_TYPE_USB3>;
 			phy-names = "pcie-phy";
 
 			ranges = <0x02000000 0 0x28000000 0x0 0x28000000 0 0x4000000>;