From: Alexander Ivchenko Date: Fri, 11 Oct 2013 13:42:10 +0000 (+0000) Subject: sse.md (VI2_AVX512F): New. X-Git-Tag: releases/gcc-4.9.0~3579 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3bdf634051b1b7f5dbb21e7a1388baaf78619c23;p=thirdparty%2Fgcc.git sse.md (VI2_AVX512F): New. * config/i386/sse.md (VI2_AVX512F): New. (VI124_AVX512F): Ditto. (sseunpackmode): Extended with wider modes. (sseunpackfltmode): Ditto. (vec_unpacks_float_hi_): Ditto. (vec_unpacks_float_lo_): Ditto. (vec_unpacku_float_hi_): Ditto. (vec_unpacku_float_lo_): Ditto. (vec_unpacks_lo_): Ditto. (vec_unpacks_hi_): Ditto. (vec_unpacku_lo_): Ditto. (vec_unpacku_hi_): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r203433 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c57fa68e3654..93da34dcabeb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2013-10-11 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (VI2_AVX512F): New. + (VI124_AVX512F): Ditto. + (sseunpackmode): Extended with wider modes. + (sseunpackfltmode): Ditto. + (vec_unpacks_float_hi_): Ditto. + (vec_unpacks_float_lo_): Ditto. + (vec_unpacku_float_hi_): Ditto. + (vec_unpacku_float_lo_): Ditto. + (vec_unpacks_lo_): Ditto. + (vec_unpacks_hi_): Ditto. + (vec_unpacku_lo_): Ditto. + (vec_unpacku_hi_): Ditto. + 2013-10-11 Alexander Ivchenko Maxim Kuznetsov Sergey Lega diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 89c31c5c0bb1..351f5bb59564 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -201,6 +201,9 @@ (define_mode_iterator VI2_AVX2 [(V16HI "TARGET_AVX2") V8HI]) +(define_mode_iterator VI2_AVX512F + [(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI]) + (define_mode_iterator VI4_AVX2 [(V8SI "TARGET_AVX2") V4SI]) @@ -223,6 +226,11 @@ [(V16HI "TARGET_AVX2") V8HI (V8SI "TARGET_AVX2") V4SI]) +(define_mode_iterator VI124_AVX512F + [(V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI]) + (define_mode_iterator VI124_AVX2 [(V32QI "TARGET_AVX2") V16QI (V16HI "TARGET_AVX2") V8HI @@ -472,7 +480,8 @@ ;; Pack/unpack vector modes (define_mode_attr sseunpackmode [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") - (V32QI "V16HI") (V16HI "V8SI") (V8SI "V4DI")]) + (V32QI "V16HI") (V16HI "V8SI") (V8SI "V4DI") + (V32HI "V16SI") (V64QI "V32HI") (V16SI "V8DI")]) (define_mode_attr ssepackmode [(V8HI "V16QI") (V4SI "V8HI") (V2DI "V4SI") @@ -3347,11 +3356,12 @@ "TARGET_AVX") (define_mode_attr sseunpackfltmode - [(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") (V8SI "V4DF")]) + [(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") + (V8SI "V4DF") (V32HI "V16SF") (V16SI "V8DF")]) (define_expand "vec_unpacks_float_hi_" [(match_operand: 0 "register_operand") - (match_operand:VI2_AVX2 1 "register_operand")] + (match_operand:VI2_AVX512F 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (mode); @@ -3364,7 +3374,7 @@ (define_expand "vec_unpacks_float_lo_" [(match_operand: 0 "register_operand") - (match_operand:VI2_AVX2 1 "register_operand")] + (match_operand:VI2_AVX512F 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (mode); @@ -3377,7 +3387,7 @@ (define_expand "vec_unpacku_float_hi_" [(match_operand: 0 "register_operand") - (match_operand:VI2_AVX2 1 "register_operand")] + (match_operand:VI2_AVX512F 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (mode); @@ -3390,7 +3400,7 @@ (define_expand "vec_unpacku_float_lo_" [(match_operand: 0 "register_operand") - (match_operand:VI2_AVX2 1 "register_operand")] + (match_operand:VI2_AVX512F 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (mode); @@ -7835,25 +7845,25 @@ (define_expand "vec_unpacks_lo_" [(match_operand: 0 "register_operand") - (match_operand:VI124_AVX2 1 "register_operand")] + (match_operand:VI124_AVX512F 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;") (define_expand "vec_unpacks_hi_" [(match_operand: 0 "register_operand") - (match_operand:VI124_AVX2 1 "register_operand")] + (match_operand:VI124_AVX512F 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;") (define_expand "vec_unpacku_lo_" [(match_operand: 0 "register_operand") - (match_operand:VI124_AVX2 1 "register_operand")] + (match_operand:VI124_AVX512F 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;") (define_expand "vec_unpacku_hi_" [(match_operand: 0 "register_operand") - (match_operand:VI124_AVX2 1 "register_operand")] + (match_operand:VI124_AVX512F 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")