From: Peng Fan Date: Tue, 4 Nov 2025 10:05:52 +0000 (+0800) Subject: remoteproc: imx_rproc: Support i.MX8MQ/M X-Git-Tag: v2026.01-rc2~39^2~18 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3c2e6002f55cbb039a59c0cf9672daec9cfacb62;p=thirdparty%2Fu-boot.git remoteproc: imx_rproc: Support i.MX8MQ/M i.MX8MQ/M use MMIO based method to directly configure SRC registers to start/stop M4. Add mmio ops to start/stop/is_running. Add i.MX8MQ cfg data, i.MX8MN reuses i.MX8MQ data. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c index 1b2ef5005e3..c71e409a00a 100644 --- a/drivers/remoteproc/imx_rproc.c +++ b/drivers/remoteproc/imx_rproc.c @@ -9,10 +9,27 @@ #include #include #include +#include #include +#include #include "imx_rproc.h" +#define IMX7D_SRC_SCR 0x0C +#define IMX7D_ENABLE_M4 BIT(3) +#define IMX7D_SW_M4P_RST BIT(2) +#define IMX7D_SW_M4C_RST BIT(1) +#define IMX7D_SW_M4C_NON_SCLR_RST BIT(0) + +#define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ + | IMX7D_SW_M4C_RST \ + | IMX7D_SW_M4C_NON_SCLR_RST) + +#define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ + | IMX7D_SW_M4C_RST) +#define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \ + IMX7D_SW_M4C_NON_SCLR_RST) + #define IMX_RPROC_MEM_MAX 32 #define IMX_SIP_RPROC 0xC2000005 @@ -22,6 +39,7 @@ struct imx_rproc { const struct imx_rproc_dcfg *dcfg; + struct regmap *regmap; }; /* att flags: lower 16 bits specifying core, higher 16 bits for flags */ @@ -38,6 +56,14 @@ static int imx_rproc_arm_smc_start(struct udevice *dev) return res.a0; } +static int imx_rproc_mmio_start(struct udevice *dev) +{ + struct imx_rproc *priv = dev_get_priv(dev); + const struct imx_rproc_dcfg *dcfg = priv->dcfg; + + return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_start); +} + static int imx_rproc_start(struct udevice *dev) { struct imx_rproc *priv = dev_get_priv(dev); @@ -65,6 +91,14 @@ static int imx_rproc_arm_smc_stop(struct udevice *dev) return res.a0; } +static int imx_rproc_mmio_stop(struct udevice *dev) +{ + struct imx_rproc *priv = dev_get_priv(dev); + const struct imx_rproc_dcfg *dcfg = priv->dcfg; + + return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_stop); +} + static int imx_rproc_stop(struct udevice *dev) { struct imx_rproc *priv = dev_get_priv(dev); @@ -92,6 +126,25 @@ static int imx_rproc_arm_smc_is_running(struct udevice *dev) return 1; } +static int imx_rproc_mmio_is_running(struct udevice *dev) +{ + struct imx_rproc *priv = dev_get_priv(dev); + const struct imx_rproc_dcfg *dcfg = priv->dcfg; + int ret; + u32 val; + + ret = regmap_read(priv->regmap, dcfg->src_reg, &val); + if (ret) { + dev_err(dev, "Failed to read src\n"); + return ret; + } + + if ((val & dcfg->src_mask) != dcfg->src_stop) + return 0; + + return 1; +} + static int imx_rproc_is_running(struct udevice *dev) { struct imx_rproc *priv = dev_get_priv(dev); @@ -171,6 +224,15 @@ static int imx_rproc_probe(struct udevice *dev) priv->dcfg = dcfg; + if (dcfg->method != IMX_RPROC_MMIO) + return 0; + + priv->regmap = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(priv->regmap)) { + dev_err(dev, "No syscon: %ld\n", PTR_ERR(priv->regmap)); + return PTR_ERR(priv->regmap); + } + return 0; } @@ -217,9 +279,54 @@ static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn = { .ops = &imx_rproc_ops_arm_smc, }; +static const struct imx_rproc_att imx_rproc_att_imx8mq[] = { + /* dev addr , sys addr , size , flags */ + /* TCML - alias */ + { 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM}, + /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x00008000, 0 }, + /* OCRAM */ + { 0x00900000, 0x00900000, 0x00020000, 0 }, + /* OCRAM */ + { 0x00920000, 0x00920000, 0x00020000, 0 }, + /* QSPI Code - alias */ + { 0x08000000, 0x08000000, 0x08000000, 0 }, + /* DDR (Code) - alias */ + { 0x10000000, 0x40000000, 0x0FFE0000, 0 }, + /* TCML/U */ + { 0x1FFE0000, 0x007E0000, 0x00040000, ATT_OWN | ATT_IOMEM}, + /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x00008000, ATT_OWN }, + /* OCRAM */ + { 0x20200000, 0x00900000, 0x00020000, ATT_OWN }, + /* OCRAM */ + { 0x20220000, 0x00920000, 0x00020000, ATT_OWN }, + /* DDR (Data) */ + { 0x40000000, 0x40000000, 0x80000000, 0 }, +}; + +static const struct imx_rproc_plat_ops imx_rproc_ops_mmio = { + .start = imx_rproc_mmio_start, + .stop = imx_rproc_mmio_stop, + .is_running = imx_rproc_mmio_is_running, +}; + +static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = { + .src_reg = IMX7D_SRC_SCR, + .src_mask = IMX7D_M4_RST_MASK, + .src_start = IMX7D_M4_START, + .src_stop = IMX7D_M4_STOP, + .att = imx_rproc_att_imx8mq, + .att_size = ARRAY_SIZE(imx_rproc_att_imx8mq), + .method = IMX_RPROC_MMIO, + .ops = &imx_rproc_ops_mmio, +}; + static const struct udevice_id imx_rproc_ids[] = { + { .compatible = "fsl,imx8mm-cm4", .data = (ulong)&imx_rproc_cfg_imx8mq }, { .compatible = "fsl,imx8mn-cm7", .data = (ulong)&imx_rproc_cfg_imx8mn, }, { .compatible = "fsl,imx8mp-cm7", .data = (ulong)&imx_rproc_cfg_imx8mn, }, + { .compatible = "fsl,imx8mq-cm4", .data = (ulong)&imx_rproc_cfg_imx8mq }, {} };