From: Julian Seward <jseward@acm.org>
Date: Wed, 7 May 2014 09:41:40 +0000 (+0000)
Subject: Enable 'smulh'.
X-Git-Tag: svn/VALGRIND_3_10_1^2~114
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3c5c41b865a542b81bad7ad0dde0c77362e0ed3e;p=thirdparty%2Fvalgrind.git

Enable 'smulh'.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2856
---

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 55ca7e24d1..57a2d4f8e7 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -2373,8 +2373,7 @@ Bool dis_ARM64_data_processing_register(/*MB_OUT*/DisResult* dres,
       10011011 0  10 Rm 011111 Rn Rd   SMULH Xd,Xn,Xm
    */
    if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1)
-       && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1)
-       && INSN(23,23) == 1/*ATC*/) {
+       && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1)) {
       Bool isU = INSN(23,23) == 1;
       UInt mm  = INSN(20,16);
       UInt nn  = INSN(9,5);
diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c
index 8aa27e6252..3bc52172f8 100644
--- a/VEX/priv/host_arm64_defs.c
+++ b/VEX/priv/host_arm64_defs.c
@@ -4591,9 +4591,9 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             case ARM64mul_ZX:
                *p++ = X_3_8_5_6_5_5(X100, X11011110, mm, X011111, nn, dd);
                goto done;
-            //case ARM64mul_SX:
-            //   *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd);
-            //   goto done;
+            case ARM64mul_SX:
+               *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd);
+               goto done;
             case ARM64mul_PLAIN:
                *p++ = X_3_8_5_6_5_5(X100, X11011000, mm, X011111, nn, dd);
                goto done;
diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index c54c973365..eb06cdfe9d 100644
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -2408,7 +2408,7 @@ static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
       switch (e->Iex.Binop.op) {
          /* 64 x 64 -> 128 multiply */
          case Iop_MullU64:
-         /*case Iop_MullS64:*/ {
+         case Iop_MullS64: {
             Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
             HReg argL  = iselIntExpr_R(env, e->Iex.Binop.arg1);
             HReg argR  = iselIntExpr_R(env, e->Iex.Binop.arg2);