From: Haochen Jiang <haochen.jiang@intel.com>
Date: Tue, 8 Feb 2022 02:51:26 +0000 (+0800)
Subject: i386: Add combine splitter to transform pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest.
X-Git-Tag: basepoints/gcc-14~6869
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3c9364f29e7e47eb9de33f2d8843d5b00284ceca;p=thirdparty%2Fgcc.git

i386: Add combine splitter to transform pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest.

gcc/ChangeLog:

	PR target/104371
	* config/i386/sse.md (vi1avx2const): New define_mode_attr.
	(pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest splitter):
	New define_split pattern.

gcc/testsuite/ChangeLog:

	PR target/104371
	* gcc.target/i386/pr104371-1.c: New test.
	* gcc.target/i386/pr104371-2.c: Ditto.
---

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a63df0d0b1f..6578104fee2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -20177,6 +20177,24 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "SI")])
 
+;; Optimize pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest.
+(define_mode_attr vi1avx2const
+  [(V32QI "0xffffffff") (V16QI "0xffff")])
+
+(define_split
+  [(set (reg:CCZ FLAGS_REG)
+	(compare:CCZ (unspec:SI
+			[(eq:VI1_AVX2
+			    (match_operand:VI1_AVX2 0 "vector_operand")
+			    (match_operand:VI1_AVX2 1 "const0_operand"))]
+		    UNSPEC_MOVMSK)
+		 (match_operand 2 "const_int_operand")))]
+  "TARGET_SSE4_1 && (INTVAL (operands[2]) == (int) (<vi1avx2const>))"
+  [(set (reg:CC FLAGS_REG)
+	(unspec:CC [(match_dup 0)
+		    (match_dup 0)]
+		   UNSPEC_PTEST))])
+
 (define_expand "sse2_maskmovdqu"
   [(set (match_operand:V16QI 0 "memory_operand")
 	(unspec:V16QI [(match_operand:V16QI 1 "register_operand")
diff --git a/gcc/testsuite/gcc.target/i386/pr104371-1.c b/gcc/testsuite/gcc.target/i386/pr104371-1.c
new file mode 100644
index 00000000000..b4373c55ab2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104371-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+/* { dg-final { scan-assembler "ptest\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "pxor\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "pcmpeqb\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "pmovmskb\[ \\t\]" } } */
+
+#include <smmintrin.h>
+
+int is_zero(__m128i x)
+{
+  return _mm_movemask_epi8(_mm_cmpeq_epi8(x, _mm_setzero_si128())) == 0xffff;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr104371-2.c b/gcc/testsuite/gcc.target/i386/pr104371-2.c
new file mode 100755
index 00000000000..3431ffc1cc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104371-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-final { scan-assembler "vptest\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "vpxor\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "vpcmpeqb\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "vpmovmskb\[ \\t\]" } } */
+
+#include <immintrin.h>
+
+int is_zero256(__m256i x)
+{
+  return _mm256_movemask_epi8(_mm256_cmpeq_epi8(x, _mm256_setzero_si256())) == 0xffffffff;
+}