From: Petar Jovanovic <mips32r2@gmail.com>
Date: Tue, 16 Jun 2015 23:40:21 +0000 (+0000)
Subject: mips64: add support for Cavium LHX
X-Git-Tag: svn/VALGRIND_3_11_0^2~39
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3cb25d709e4b1f4d0d6dfb3f436364fe89d318c2;p=thirdparty%2Fvalgrind.git

mips64: add support for Cavium LHX

This patch adds support for LHX (Load Halfword Indexed) instruction.
It is available on CVMv2/MIPS DSP.

Issue reported in BZ #345987.

Patch by Crestez Dan Leonard.


git-svn-id: svn://svn.valgrind.org/vex/trunk@3152
---

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 8e94298142..84d2608ff5 100644
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -2638,6 +2638,16 @@ static Bool dis_instr_CVM ( UInt theInstr )
                                                   True));
                      break;
                   }
+                  case 0x04:  // LHX rd, index(base)
+                     DIP("lhx r%d, r%d(r%d)", regRd, regRt, regRs);
+                     LOADX_STORE_PATTERN;
+                     if (mode64)
+                        putIReg(regRd, unop(Iop_16Sto64, load(Ity_I16,
+                                                              mkexpr(t1))));
+                     else
+                        putIReg(regRd, unop(Iop_16Sto32, load(Ity_I16,
+                                                              mkexpr(t1))));
+                     break;
                   case 0x08: {  // LDX rd, index(base)
                      DIP("ldx r%d, r%d(r%d)", regRd, regRt, regRs);
                      vassert(mode64); /* Currently Implemented only for n64 */