From: Pan Li Date: Wed, 16 Aug 2023 12:47:38 +0000 (+0800) Subject: RISC-V: Support RVV VFNCVT.X.F.W rounding mode intrinsic API X-Git-Tag: basepoints/gcc-15~6869 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3d18a528bfd05f0bfdb27f52c2f6c2445f15e4ca;p=thirdparty%2Fgcc.git RISC-V: Support RVV VFNCVT.X.F.W rounding mode intrinsic API This patch would like to support the rounding mode API for the VFNCVT.X.F.W as the below samples. * __riscv_vfncvt_x_f_w_i16mf2_rm * __riscv_vfncvt_x_f_w_i16mf2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfncvt_x): Add frm_op_type template arg. (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfncvt_x_frm): New intrinsic function def. * config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_frm_def): New shape function for frm. (SHAPE): New declaration. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-ncvt-x.c: New test. --- diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 050ecbe780c9..2f40eeaeda5c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1759,10 +1759,15 @@ public: }; /* Implements vfncvt.x. */ -template +template class vfncvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn ( @@ -2502,6 +2507,7 @@ static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj; static CONSTEXPR const vfwcvt_f vfwcvt_f_obj; static CONSTEXPR const vfncvt_x vfncvt_x_obj; +static CONSTEXPR const vfncvt_x vfncvt_x_frm_obj; static CONSTEXPR const vfncvt_x vfncvt_xu_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; @@ -2756,6 +2762,7 @@ BASE (vfwcvt_rtz_x) BASE (vfwcvt_rtz_xu) BASE (vfwcvt_f) BASE (vfncvt_x) +BASE (vfncvt_x_frm) BASE (vfncvt_xu) BASE (vfncvt_rtz_x) BASE (vfncvt_rtz_xu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 6565740c5977..edff0de27155 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -220,6 +220,7 @@ extern const function_base *const vfwcvt_rtz_x; extern const function_base *const vfwcvt_rtz_xu; extern const function_base *const vfwcvt_f; extern const function_base *const vfncvt_x; +extern const function_base *const vfncvt_x_frm; extern const function_base *const vfncvt_xu; extern const function_base *const vfncvt_rtz_x; extern const function_base *const vfncvt_rtz_xu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 22c039c8cbb9..5e37bae318a5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -472,6 +472,8 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, u_to_nf_xu_w_ops) DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, f_to_nf_f_w_ops) DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops) +DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops) + /* 14. Vector Reduction Operations. */ // 14.1. Vector Single-Width Integer Reduction Instructions diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 1d14fa21e81c..80329113af33 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -333,6 +333,44 @@ struct widen_alu_frm_def : public build_frm_base } }; +/* narrow_alu_frm_def class. */ +struct narrow_alu_frm_def : public build_frm_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + char base_name[BASE_NAME_MAX_LEN] = {}; + + normalize_base_name (base_name, instance.base_name, sizeof (base_name)); + + b.append_base_name (base_name); + + if (!overloaded_p) + { + /* vop --> vop_. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_ --> vop__. */ + vector_type_index ret_type_idx + = instance.op_info->ret.get_function_type_index (instance.type.index); + b.append_name (type_suffixes[ret_type_idx].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_rm" suffix + for vop_rm C++ overloaded API. */ + if (!overloaded_p) + b.append_name ("_rm"); + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + + b.append_name (predication_suffixes[instance.pred]); + + return b.finish_name (); + } +}; + /* widen_alu_def class. Handle vwadd/vwsub. Unlike vadd.vx/vadd.vv/vwmul.vv/vwmul.vx, vwadd.vv/vwadd.vx/vwadd.wv/vwadd.wx has 'OP' suffix in overloaded API. */ @@ -856,6 +894,7 @@ SHAPE(widen_alu_frm, widen_alu_frm) SHAPE(no_mask_policy, no_mask_policy) SHAPE(return_mask, return_mask) SHAPE(narrow_alu, narrow_alu) +SHAPE(narrow_alu_frm, narrow_alu_frm) SHAPE(move, move) SHAPE(mask_alu, mask_alu) SHAPE(reduc_alu, reduc_alu) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index 841b930b5475..b53ab451902e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -35,6 +35,7 @@ extern const function_shape *const widen_alu_frm; extern const function_shape *const no_mask_policy; extern const function_shape *const return_mask; extern const function_shape *const narrow_alu; +extern const function_shape *const narrow_alu_frm; extern const function_shape *const move; extern const function_shape *const mask_alu; extern const function_shape *const reduc_alu; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c new file mode 100644 index 000000000000..1630b7e7ccf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vint16mf2_t +test_riscv_vfncvt_x_f_w_i16mf2_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_rm (op1, 0, vl); +} + +vint16mf2_t +test_vfncvt_x_f_w_i16mf2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_rm_m (mask, op1, 1, vl); +} + +vint16mf2_t +test_riscv_vfncvt_x_f_w_i16mf2 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2 (op1, vl); +} + +vint16mf2_t +test_vfncvt_x_f_w_i16mf2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfncvt\.x\.f\.w\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */