From: Greg Kroah-Hartman Date: Wed, 11 Feb 2026 11:56:46 +0000 (+0100) Subject: 6.1-stable patches X-Git-Tag: v5.10.250~2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3d268ac8a00367c591a310cc7d11ba46dafd8d4d;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: riscv-replace-function-like-macro-by-static-inline-function.patch --- diff --git a/queue-6.1/riscv-replace-function-like-macro-by-static-inline-function.patch b/queue-6.1/riscv-replace-function-like-macro-by-static-inline-function.patch new file mode 100644 index 0000000000..8e927524a1 --- /dev/null +++ b/queue-6.1/riscv-replace-function-like-macro-by-static-inline-function.patch @@ -0,0 +1,60 @@ +From 0b1ac9743f3d9cfced2ac3cb9f274c0675bd4189 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= +Date: Sat, 19 Apr 2025 13:13:59 +0200 +Subject: riscv: Replace function-like macro by static inline function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Björn Töpel + +commit 121f34341d396b666d8a90b24768b40e08ca0d61 upstream. + +The flush_icache_range() function is implemented as a "function-like +macro with unused parameters", which can result in "unused variables" +warnings. + +Replace the macro with a static inline function, as advised by +Documentation/process/coding-style.rst. + +Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable") +Signed-off-by: Björn Töpel +Link: https://lore.kernel.org/r/20250419111402.1660267-1-bjorn@kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Ron Economos +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/include/asm/cacheflush.h | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -22,11 +22,6 @@ static inline void flush_dcache_page(str + } + #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 + +-/* +- * RISC-V doesn't have an instruction to flush parts of the instruction cache, +- * so instead we just flush the whole thing. +- */ +-#define flush_icache_range(start, end) flush_icache_all() + #define flush_icache_user_page(vma, pg, addr, len) \ + flush_icache_mm(vma->vm_mm, 0) + +@@ -42,6 +37,16 @@ void flush_icache_mm(struct mm_struct *m + + #endif /* CONFIG_SMP */ + ++/* ++ * RISC-V doesn't have an instruction to flush parts of the instruction cache, ++ * so instead we just flush the whole thing. ++ */ ++#define flush_icache_range flush_icache_range ++static inline void flush_icache_range(unsigned long start, unsigned long end) ++{ ++ flush_icache_all(); ++} ++ + extern unsigned int riscv_cbom_block_size; + void riscv_init_cbom_blocksize(void); + diff --git a/queue-6.1/series b/queue-6.1/series index 7576cc2f31..c7203a1158 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -67,3 +67,4 @@ spi-tegra210-quad-protect-curr_xfer-in-tegra_qspi_co.patch spi-tegra210-quad-protect-curr_xfer-clearing-in-tegr.patch spi-tegra-fix-a-memory-leak-in-tegra_slink_probe.patch alsa-hda-realtek-really-fix-headset-mic-for-tongfang-x6ar55xu.patch +riscv-replace-function-like-macro-by-static-inline-function.patch