From: Jeffrey Yu <jeyu@issi.com>
Date: Mon, 23 Feb 2026 20:59:24 +0000 (+0000)
Subject: mtd: spi-nor: ids: add ISSI IS25LP*J/*MJ/*E and IS25WP*J/*MJ device IDs
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3d623b9d39c167ba58fe2e04650a9ddfc4d8c55e;p=thirdparty%2Fu-boot.git

mtd: spi-nor: ids: add ISSI IS25LP*J/*MJ/*E and IS25WP*J/*MJ device IDs

Add JEDEC ID table entries for additional ISSI SPI-NOR devices.

These parts previously not yet supported.
With these entries, U-Boot can match the device by JEDEC ID
and use the existing ISSI SPI-NOR device handling.

Newly added devices include:
  - IS25LP512MJ  (JEDEC 0x9d6020)
    https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf
  - IS25WP512MJ  (JEDEC 0x9d7020)
    https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf
  - IS25LP010E   (JEDEC 0x9d4011)
    https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
  - IS25LP020E   (JEDEC 0x9d4012)
    https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
  - IS25LP040E   (JEDEC 0x9d4013)
    https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
  - IS25LP01GJ   (JEDEC 0x9d6021)
    https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf
  - IS25LP02GG   (JEDEC 0x9d6022)
    https://www.issi.com/WW/pdf/25LP-WP02GG.pdf
  - IS25LP02GJ   (JEDEC 0x9d6022)
    https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf
  - IS25WP01GG   (JEDEC 0x9d7021)
    https://www.issi.com/WW/pdf/25LP-WP01GG.pdf
  - IS25WP01GJ   (JEDEC 0x9d7021)
    https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf
  - IS25WJ128F   (JEDEC 0x9d7118)
    https://www.issi.com/WW/pdf/25WJ128F.pdf
  - IS25WP02GG   (JEDEC 0x9d7022)
    https://www.issi.com/WW/pdf/25LP-WP02GG.pdf
  - IS25WP02GJ   (JEDEC 0x9d7022)
    https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf

Signed-off-by: jeffrey yu <jeyu@issi.com>
[trini: Fix spacing issues]
Signed-off-by: Tom Rini <trini@konsulko.com>
---

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 43dc628f74a..700738a374a 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -244,6 +244,8 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ) },
 	{ INFO("is25lp512",  0x9d601a, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp512mj", 0x9d6020, 0, 64 * 1024, 1024,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25lp01g",  0x9d601b, 0, 64 * 1024, 2048,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25wp008", 0x9d7014, 0, 64 * 1024,  16, SPI_NOR_QUAD_READ) },
@@ -259,6 +261,8 @@ const struct flash_info spi_nor_ids[] = {
 			SPI_NOR_4B_OPCODES) },
 	{ INFO("is25wp512",  0x9d701a, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25wp512mj", 0x9d7020, 0, 64 * 1024, 1024,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25wp01g",  0x9d701b, 0, 64 * 1024, 2048,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25wx256",  0x9d5b19, 0, 128 * 1024, 256,
@@ -267,8 +271,28 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) },
 	{ INFO("is25lp01gg",  0x9d6021, 0, 64 * 1024, 2048,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25lp010e",  0x9d4011, 0, 64 * 1024, 2,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp020e",  0x9d4012, 0, 64 * 1024, 4,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp040e",  0x9d4013, 0, 64 * 1024, 8,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp01gj",  0x9d6021, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25lp02gg",  0x9d6022, 0, 64 * 1024, 4096,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25lp02gj",  0x9d6022, 0, 64 * 1024, 4096,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25wp01gg",  0x9d7021, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25wp01gj",  0x9d7021, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25wj128f",  0x9d7118, 0, 64 * 1024, 256,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
 	{ INFO("is25wp02gg",  0x9d7022, 0, 64 * 1024, 4096,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
+	{ INFO("is25wp02gj",  0x9d7022, 0, 64 * 1024, 4096,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
 	/* Macronix */