From: Uros Bizjak Date: Thu, 17 Feb 2011 21:22:02 +0000 (+0100) Subject: re PR target/43653 (ICE at reload1.c:1188 with -O1 -ftree-vectorize and empty struct) X-Git-Tag: releases/gcc-4.5.3~220 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3d7c1f3a3991a45722dc4f46807b656ed2a5d4eb;p=thirdparty%2Fgcc.git re PR target/43653 (ICE at reload1.c:1188 with -O1 -ftree-vectorize and empty struct) PR target/43653 * config/i386/i386.c (ix86_secondary_reload): Handle SSE input reload with PLUS RTX. testsuite/ChangeLog: PR target/43653 * gcc.target/i386/pr43653.c: New test. From-SVN: r170256 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a454199befb..b55a0ac4c70f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-02-17 Uros Bizjak + + PR target/43653 + * config/i386/i386.c (ix86_secondary_reload): Handle SSE + input reload with PLUS RTX. + 2011-02-15 Rainer Orth PR pch/14940 @@ -285,9 +291,9 @@ Backport from mainline: 2010-12-30 Nathan Froyd - PR target/44606 - * reload1.c (choose_reload_regs): Don't look for equivalences for - output reloads of constant loads. + PR target/44606 + * reload1.c (choose_reload_regs): Don't look for equivalences for + output reloads of constant loads. 2011-01-30 Gerald Pfeifer @@ -313,7 +319,7 @@ Backport from mainline: 2010-08-22 John David Anglin - PR boehm-gc/34544 + PR boehm-gc/34544 * gthr-posix.h (__gthread_active_init): Delete. (__gthread_active_p): Do activity check here. Don't include errno.h on hppa-hpux. Update comment. @@ -412,8 +418,8 @@ (avx_maskstore): Likewise. 2011-01-17 Olivier Hainque - Michael Haubenwallner - Eric Botcazou + Michael Haubenwallner + Eric Botcazou PR target/46655 * xcoffout.c (ASM_OUTPUT_LINE): Output line only if positive, and only @@ -566,7 +572,7 @@ Backport from mainline Fix PR45758: reset scevs before Graphite. - 2010-09-24 Sebastian Pop + 2010-09-24 Sebastian Pop PR tree-optimization/45552 * graphite.c (graphite_initialize): Call scev_reset. @@ -770,7 +776,7 @@ Backport from mainline: 2010-09-15 Olivier Hainque - Jose Ruiz + Jose Ruiz * config/alpha/osf.h (MD_UNWIND_SUPPORT): Define. * config/alpha/osf-unwind.h: New file. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 29ef16d7753b..c2a46502c813 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -25137,7 +25137,8 @@ ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass, { /* QImode spills from non-QI registers require intermediate register on 32bit targets. */ - if (!in_p && mode == QImode && !TARGET_64BIT + if (!TARGET_64BIT + && !in_p && mode == QImode && (rclass == GENERAL_REGS || rclass == LEGACY_REGS || rclass == INDEX_REGS)) @@ -25157,6 +25158,45 @@ ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass, return Q_REGS; } + /* This condition handles corner case where an expression involving + pointers gets vectorized. We're trying to use the address of a + stack slot as a vector initializer. + + (set (reg:V2DI 74 [ vect_cst_.2 ]) + (vec_duplicate:V2DI (reg/f:DI 20 frame))) + + Eventually frame gets turned into sp+offset like this: + + (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) + (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp) + (const_int 392 [0x188])))) + + That later gets turned into: + + (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) + (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp) + (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64])))) + + We'll have the following reload recorded: + + Reload 0: reload_in (DI) = + (plus:DI (reg/f:DI 7 sp) + (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64])) + reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) + SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine + reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188])) + reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) + reload_reg_rtx: (reg:V2DI 22 xmm1) + + Which isn't going to work since SSE instructions can't handle scalar + additions. Returning GENERAL_REGS forces the addition into integer + register and reload can handle subsequent reloads without problems. */ + + if (in_p && GET_CODE (x) == PLUS + && SSE_CLASS_P (rclass) + && SCALAR_INT_MODE_P (mode)) + return GENERAL_REGS; + return NO_REGS; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 35c7fb9291c5..c312246053c4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-02-17 Uros Bizjak + + PR target/43653 + * gcc.target/i386/pr43653.c: New test. + 2011-02-14 Tobias Burnus * gfortran.dg/argument_checking_13.f90: Update dg-error. @@ -62,8 +67,8 @@ Backport from mainline: 2010-12-30 Nathan Froyd - PR target/44606 - * gcc.dg/pr44606.c: New test. + PR target/44606 + * gcc.dg/pr44606.c: New test. 2011-01-27 Andreas Krebbel @@ -278,7 +283,7 @@ Backport from mainline 2010-12-06 Jakub Jelinek - + PR target/43897 * gcc.target/ia64/pr43897.c: New test. @@ -297,7 +302,7 @@ * gcc.dg/pr46499-2.c: New test. 2010-11-20 Jakub Jelinek - + PR c++/46538 * g++.dg/other/error34.C: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr43653.c b/gcc/testsuite/gcc.target/i386/pr43653.c new file mode 100644 index 000000000000..22928edacfec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr43653.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -ftree-vectorize -msse" } */ + +typedef struct {} S; + +void *foo() +{ + S a[64], *p[64]; + int i; + + for (i = 0; i < 64; i++) + p[i] = &a[i]; + return p[0]; +}