From: Ulrich Drepper <drepper@redhat.com>
Date: Thu, 23 Jul 2009 20:42:46 +0000 (-0700)
Subject: Add more cache descriptors for L3 caches on x86 and x86-64.
X-Git-Tag: fedora/glibc-2.10.90-9~1^2~17
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3e9099b4f6666cd05b62d2829f65161daddb151b;p=thirdparty%2Fglibc.git

Add more cache descriptors for L3 caches on x86 and x86-64.

The most recent AP 485 describes a few more cache descriptors for
L3 caches with 24-way associativity.
---

diff --git a/ChangeLog b/ChangeLog
index 1498e4a3c09..29e4468ce41 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,9 @@
 2009-07-23  Ulrich Drepper  <drepper@redhat.com>
 
+	* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Add more
+	cache descriptors.
+	* sysdeps/x86_64/cacheinfo.c (intel_02_known): Likewise.
+
 	* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Reset
 	SSSE3 bit for Atoms.
 	* sysdeps/x86_64/multiarch/strcpy.S: New need to perform Atom test
diff --git a/sysdeps/unix/sysv/linux/i386/sysconf.c b/sysdeps/unix/sysv/linux/i386/sysconf.c
index efe1a639cd2..ff3cf9f7c76 100644
--- a/sysdeps/unix/sysv/linux/i386/sysconf.c
+++ b/sysdeps/unix/sysv/linux/i386/sysconf.c
@@ -138,6 +138,9 @@ static const struct intel_02_cache_info
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
     { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
+    { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
+    { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
+    { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
   };
 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 362687c1815..07939099b93 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -100,6 +100,9 @@ static const struct intel_02_cache_info
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
     { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
+    { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
+    { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
+    { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
   };
 
 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0]))