From: Bill Schmidt Date: Wed, 9 Apr 2014 20:07:55 +0000 (+0000) Subject: Revert following patch 2014-04-08 Pat Haugen X-Git-Tag: releases/gcc-4.8.3~158 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3edfe0c1281b31bfd12e86e900b839af2bff2114;p=thirdparty%2Fgcc.git Revert following patch 2014-04-08 Pat Haugen 2014-04-09 Bill Schmidt Revert following patch 2014-04-08 Pat Haugen Backport from mainline 2014-04-08 Pat Haugen * config/rs6000/sync.md (AINT mode_iterator): Move definition. (loadsync_): Change mode. (load_quadpti, store_quadpti): New. (atomic_load, atomic_store): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. From-SVN: r209254 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2b7ac203b31d..5f8c63824706 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2014-04-09 Bill Schmidt + + Revert following patch + 2014-04-08 Pat Haugen + + Backport from mainline + 2014-04-08 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + 2014-04-09 Bill Schmidt Backport from mainline r202642 diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index d798fa0f0f2b..3ffdde8fa652 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -633,14 +633,14 @@ (match_test "offsettable_nonstrict_memref_p (op)"))) ;; Return 1 if the operand is suitable for load/store quad memory. -;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). +;; This predicate only checks for non-atomic loads/stores. (define_predicate "quad_memory_operand" (match_code "mem") { rtx addr, op0, op1; int ret; - if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) + if (!TARGET_QUAD_MEMORY) ret = 0; else if (!memory_operand (op, mode)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a619d924a260..23c7d4cda029 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -124,7 +124,6 @@ UNSPEC_P8V_MTVSRD UNSPEC_P8V_XXPERMDI UNSPEC_P8V_RELOAD_FROM_VSX - UNSPEC_LSQ ]) ;; diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index ae027392f96d..8357f951f9bd 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -107,17 +107,10 @@ "isync" [(set_attr "type" "isync")]) -;; Types that we should provide atomic instructions for. -(define_mode_iterator AINT [QI - HI - SI - (DI "TARGET_POWERPC64") - (TI "TARGET_SYNC_TI")]) - ;; The control dependency used for load dependency described ;; in B.2.3 of the Power ISA 2.06B. (define_insn "loadsync_" - [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")] + [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")] UNSPECV_ISYNC) (clobber (match_scratch:CC 1 "=y"))] "" @@ -125,56 +118,18 @@ [(set_attr "type" "isync") (set_attr "length" "12")]) -(define_insn "load_quadpti" - [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") - (unspec:PTI - [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))] - "TARGET_SYNC_TI - && !reg_mentioned_p (operands[0], operands[1])" - "lq %0,%1" - [(set_attr "type" "load") - (set_attr "length" "4")]) - (define_expand "atomic_load" - [(set (match_operand:AINT 0 "register_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "")) ;; memory + [(set (match_operand:INT1 0 "register_operand" "") ;; output + (match_operand:INT1 1 "memory_operand" "")) ;; memory (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { - if (mode == TImode && !TARGET_SYNC_TI) - FAIL; - enum memmodel model = (enum memmodel) INTVAL (operands[2]); if (model == MEMMODEL_SEQ_CST) emit_insn (gen_hwsync ()); - if (mode != TImode) - emit_move_insn (operands[0], operands[1]); - else - { - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx pti_reg = gen_reg_rtx (PTImode); - - // Can't have indexed address for 'lq' - if (indexed_address (XEXP (op1, 0), TImode)) - { - rtx old_addr = XEXP (op1, 0); - rtx new_addr = force_reg (Pmode, old_addr); - operands[1] = op1 = replace_equiv_address (op1, new_addr); - } - - emit_insn (gen_load_quadpti (pti_reg, op1)); - - if (WORDS_BIG_ENDIAN) - emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); - else - { - emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg)); - emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg)); - } - } + emit_move_insn (operands[0], operands[1]); switch (model) { @@ -191,24 +146,12 @@ DONE; }) -(define_insn "store_quadpti" - [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") - (unspec:PTI - [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] - "TARGET_SYNC_TI" - "stq %1,%0" - [(set_attr "type" "store") - (set_attr "length" "4")]) - (define_expand "atomic_store" - [(set (match_operand:AINT 0 "memory_operand" "") ;; memory - (match_operand:AINT 1 "register_operand" "")) ;; input + [(set (match_operand:INT1 0 "memory_operand" "") ;; memory + (match_operand:INT1 1 "register_operand" "")) ;; input (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { - if (mode == TImode && !TARGET_SYNC_TI) - FAIL; - enum memmodel model = (enum memmodel) INTVAL (operands[2]); switch (model) { @@ -223,33 +166,7 @@ default: gcc_unreachable (); } - if (mode != TImode) - emit_move_insn (operands[0], operands[1]); - else - { - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx pti_reg = gen_reg_rtx (PTImode); - - // Can't have indexed address for 'stq' - if (indexed_address (XEXP (op0, 0), TImode)) - { - rtx old_addr = XEXP (op0, 0); - rtx new_addr = force_reg (Pmode, old_addr); - operands[0] = op0 = replace_equiv_address (op0, new_addr); - } - - if (WORDS_BIG_ENDIAN) - emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); - else - { - emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1)); - emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1)); - } - - emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg)); - } - + emit_move_insn (operands[0], operands[1]); DONE; }) @@ -263,6 +180,14 @@ SI (DI "TARGET_POWERPC64")]) +;; Types that we should provide atomic instructions for. + +(define_mode_iterator AINT [QI + HI + SI + (DI "TARGET_POWERPC64") + (TI "TARGET_SYNC_TI")]) + (define_insn "load_locked" [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") (unspec_volatile:ATOMIC diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 766d286cfe99..9cad3240eea7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,10 +1,3 @@ -2014-04-08 Pat Haugen - - Backport from mainline - 2014-04-08 Pat Haugen - - * gcc.target/powerpc/atomic_load_store-p8.c: New. - 2014-04-07 Martin Jambor PR ipa/60640 diff --git a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c index 8a5cbfaa36be..e69de29bb2d1 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c @@ -1,22 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mcpu=power8 -O2" } */ -/* { dg-final { scan-assembler-times "lq" 1 } } */ -/* { dg-final { scan-assembler-times "stq" 1 } } */ -/* { dg-final { scan-assembler-not "bl __atomic" } } */ -/* { dg-final { scan-assembler-not "lqarx" } } */ -/* { dg-final { scan-assembler-not "stqcx" } } */ - -__int128 -atomic_load_128_relaxed (__int128 *ptr) -{ - return __atomic_load_n (ptr, __ATOMIC_RELAXED); -} - -void -atomic_store_128_relaxed (__int128 *ptr, __int128 val) -{ - __atomic_store_n (ptr, val, __ATOMIC_RELAXED); -} -