From: Kevin Zhao <kevin.zhao@linaro.org>
Date: Thu, 22 Jul 2021 08:00:21 +0000 (+0800)
Subject: arm64 front end: add support for 'dc cvac', 'dc cvap', handling it the same as 'dc... 
X-Git-Tag: VALGRIND_3_24_0~149
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=40505e5056a7e434e291526d6662943e31274fc1;p=thirdparty%2Fvalgrind.git

arm64 front end: add support for 'dc cvac', 'dc cvap', handling it the same as 'dc cvau'.

patch modified to process DBP component of ID_AA64ISAR1_EL1

Signed-off-by: Kevin Zhao <kevin.zhao@linaro.org>
---

diff --git a/VEX/priv/guest_arm64_defs.h b/VEX/priv/guest_arm64_defs.h
index 55b849a7e..c9d5e9df3 100644
--- a/VEX/priv/guest_arm64_defs.h
+++ b/VEX/priv/guest_arm64_defs.h
@@ -129,6 +129,7 @@ extern ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR0_EL1 ( void );
 extern ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR1_EL1 ( void );
 
 extern ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1 ( void );
+extern ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR1_EL1 ( void );
 
 extern void  arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res,
                                          ULong arg1, ULong arg2 );
diff --git a/VEX/priv/guest_arm64_helpers.c b/VEX/priv/guest_arm64_helpers.c
index 96963dbb2..736e83620 100644
--- a/VEX/priv/guest_arm64_helpers.c
+++ b/VEX/priv/guest_arm64_helpers.c
@@ -921,6 +921,28 @@ ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1 ( void )
 #  endif
 }
 
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack.  On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR1_EL1 ( void )
+{
+#  if defined(__aarch64__) && !defined(__arm__)
+   ULong w = 0x5555555555555555ULL; /* overwritten */
+   __asm__ __volatile__("mrs %0, id_aa64isar1_el1" : "=r"(w));
+
+   // only nibble 0 DBP
+   w &= 0xF;
+   /* No dc cvadp only dc cvap */
+   if ( w & 0x2 ) {
+      w ^= 0x2;
+      w |= 0x1;
+   }
+
+   return w;
+#  else
+   return 0ULL;
+#  endif
+}
 
 void arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res, ULong arg1, ULong arg2 )
 {
diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index a6cffef81..eebe6963e 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7710,7 +7710,18 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
    */
    if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380620 /*MRS*/) {
       UInt tt    = INSN(4,0);
-      putIReg64orZR(tt, mkU64(0x0));
+      IRTemp val = newTemp(Ity_I64);
+      IRExpr** args = mkIRExprVec_0();
+      IRDirty* d    = unsafeIRDirty_1_N (
+                        val,
+                        0/*regparms*/,
+                        "arm64g_dirtyhelper_MRS_ID_AA64ISAR1_EL1",
+                        &arm64g_dirtyhelper_MRS_ID_AA64ISAR1_EL1,
+                        args
+                     );
+      /* execute the dirty call, dumping the result in val. */
+      stmt( IRStmt_Dirty(d) );
+      putIReg64orZR(tt, mkexpr(val));
       DIP("mrs %s, id_aa64isar1_el1 (FAKED)\n", nameIReg64orZR(tt));
       return True;
    }
@@ -7978,9 +7989,13 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
    /* ------------------ DC_CVAU ------------------ */
    /* D5 0B 7B 001 Rt  dc cvau, rT
       D5 0B 7E 001 Rt  dc civac, rT
+      D5 0B 7A 001 Rt  dc cvac, rT
+      D5 0B 7C 001 Rt  dc cvap, rT
    */
    if (   (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
-       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20
+       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20)
+       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20)) {
       /* Exactly the same scheme as for IC IVAU, except we observe the
          dMinLine size, and request an Ijk_FlushDCache instead of
          Ijk_InvalICache. */