From: Troy Mitchell Date: Thu, 8 Jan 2026 06:42:40 +0000 (+0800) Subject: riscv: dts: spacemit: pinctrl: update register and IO power X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4083d8d6c0aa445fc440d70a5258351c47547ee2;p=thirdparty%2Fkernel%2Flinux.git riscv: dts: spacemit: pinctrl: update register and IO power Change the size of the reg register to 0x1000 to match the hardware. This register range covers the IO power domain's register addresses. The IO power domain registers are protected. In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property `spacemit,apbc` is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com Signed-off-by: Yixun Lan --- diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index cf5802687835e..529ec68e9c23e 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -628,10 +628,11 @@ pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x400>; + reg = <0x0 0xd401e000 0x0 0x1000>; clocks = <&syscon_apbc CLK_AIB>, <&syscon_apbc CLK_AIB_BUS>; clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; }; pwm8: pwm@d4020000 {