From: Gabor Juhos Date: Mon, 28 Oct 2024 18:48:16 +0000 (+0100) Subject: clk: qcom: apps-ipq-pll: drop 'alpha_en_mask' from IPQ5332 PLL config X-Git-Tag: v6.14-rc1~150^2~2^6^2~43 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=41c5ebfb9b4b42b1479f16a50d96146fa945abce;p=thirdparty%2Fkernel%2Fstable.git clk: qcom: apps-ipq-pll: drop 'alpha_en_mask' from IPQ5332 PLL config Since neither 'alpha' nor 'alpha_hi' is defined in the configuration, those will be initialized with zero values implicitly. By using zero alpha values, the output rate of the PLL will be the same whether alpha mode is enabled or not. Remove the superfluous initialization of the 'alpha_en_mask' member to make it clear that enabling alpha mode is not required to get the desired output rate. Despite that enabling alpha mode is not needed for the initial configuration, the set_rate() op might require that it is enabled already. In this particular case however, the clk_alpha_pll_stromer_plus_set_rate() function will get reset the ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask' is safe. While at it, also add a comment to indicate the frequency the PLL runs at with the current configuration. No functional changes, the initial rate of the PLL is the same both before and after the patch. Tested on Xiaomi Router BE3600 2.5G (IPQ5312, out-of-tree board). Reviewed-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-2-9bc6d712bd76@gmail.com Signed-off-by: Bjorn Andersson --- diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index dec2a5019cc77..d6c1aea7e9e1e 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -79,13 +79,13 @@ static const struct alpha_pll_config ipq5018_pll_config = { .test_ctl_hi_val = 0x00400003, }; +/* 1.080 GHz configuration */ static const struct alpha_pll_config ipq5332_pll_config = { .l = 0x2d, .config_ctl_val = 0x4001075b, .main_output_mask = BIT(0), .aux_output_mask = BIT(1), .early_output_mask = BIT(3), - .alpha_en_mask = BIT(24), .status_val = 0x3, .status_mask = GENMASK(10, 8), .lock_det = BIT(2),