From: Uros Bizjak Date: Thu, 27 Oct 2011 06:17:00 +0000 (+0200) Subject: re PR target/37191 (ICE in inline_secondary_memory_needed, at config/i386/i386.c... X-Git-Tag: releases/gcc-4.7.0~2772 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=424c83890f0b9ddffa43ce0c89847fa88a39ab63;p=thirdparty%2Fgcc.git re PR target/37191 (ICE in inline_secondary_memory_needed, at config/i386/i386.c:21849) PR target/37191 * config/i386/sse.md (*vec_extract_v4sf_mem): Avoid combining registers from different units in a single alternative. From-SVN: r180560 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 124b17cdbe8d..8b8cea787959 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-08-27 Uros Bizjak + + PR target/37191 + * config/i386/sse.md (*vec_extract_v4sf_mem): Avoid combining registers + from different units in a single alternative. + 2011-10-26 David S. Miller * config/sparc/sparc.c (emit_scc_insn): Force attempt of v9 sequences @@ -114,8 +120,7 @@ 2011-10-26 Richard Guenther PR lto/41844 - * Makefile.in (lto-wrapper): Depend on and link against - opts-common.o. + * Makefile.in (lto-wrapper): Depend on and link against opts-common.o. (lto-wrapper.o): Depend on $(OPTS_H) and $(OPTIONS_H). * lto-wrapper.c (get_options_from_collect_gcc_options): New function. (run_gcc): Use it. Filter out language specific options. @@ -223,8 +228,7 @@ 2011-10-25 Dodji Seketeli * input.c (expand_location): Rewrite using - linemap_resolve_location and linemap_expand_location. Add a - comment. + linemap_resolve_location and linemap_expand_location. Add a comment. 2011-10-25 Jakub Jelinek @@ -265,8 +269,8 @@ to MASK_LITTLE_ENDIAN. * config/sparc/sparc.opt (Mask(LITTLE_ENDIAN)): Delete. - * config/sparc/sparc.md: Only use F, G, and C constraints in FP - insns. Only use D, Y, and Z constraints in vector insns. + * config/sparc/sparc.md: Only use F, G, and C constraints in FP insns. + Only use D, Y, and Z constraints in vector insns. * config/sparc/sparc.md (cpu_feature, enabled): New attributes. (*movsi_insn_novis3, *movsi_insn_vis3): Consolidate into one pattern @@ -343,7 +347,7 @@ 2011-10-24 Julian Brown * config/m68k/m68k.c (notice_update_cc): Tighten condition for - setting CC_REVERSED for FP comparisons. + setting CC_REVERSED for FP comparisons. 2011-10-24 Richard Guenther @@ -396,14 +400,12 @@ float and integer regs. (sparc_register_move_cost): Adjust to account for VIS3 moves. (sparc_preferred_reload_class): On 32-bit with VIS3 when moving an - integer reg to a class containing EXTRA_FP_REGS, constrain to - FP_REGS. + integer reg to a class containing EXTRA_FP_REGS, constrain to FP_REGS. (sparc_secondary_reload): On 32-bit with VIS3 when moving between float and integer regs we sometimes need a FP_REGS class intermediate move to satisfy the reload. When this happens specify an extra cost of 2. - (*movsi_insn): Rename to have "_novis3" suffix and add !VIS3 - guard. + (*movsi_insn): Rename to have "_novis3" suffix and add !VIS3 guard. (*movdi_insn_sp32_v9): Likewise. (*movdi_insn_sp64): Likewise. (*movsf_insn): Likewise. @@ -429,8 +431,7 @@ (*mov_insn_sp32_vis3): New insn. (VM64 reg<-->reg split): New spliiter for 32-bit. - * config/sparc/sparc.c (sparc_split_regreg_legitimate): New - function. + * config/sparc/sparc.c (sparc_split_regreg_legitimate): New function. * config/sparc/sparc-protos.h (sparc_split_regreg_legitimate): Declare it. * config/sparc/sparc.md (DImode reg/reg split): Use it. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 73429e472bad..740f8c856ede 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3866,6 +3866,62 @@ DONE; }) +(define_insn_and_split "*sse4_1_extractps" + [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,x,x") + (vec_select:SF + (match_operand:V4SF 1 "register_operand" "x,0,x") + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))] + "TARGET_SSE4_1" + "@ + %vextractps\t{%2, %1, %0|%0, %1, %2} + # + #" + "&& reload_completed && SSE_REG_P (operands[0])" + [(const_int 0)] +{ + rtx dest = gen_rtx_REG (V4SFmode, REGNO (operands[0])); + switch (INTVAL (operands[2])) + { + case 1: + case 3: + emit_insn (gen_sse_shufps_v4sf (dest, operands[1], operands[1], + operands[2], operands[2], + GEN_INT (INTVAL (operands[2]) + 4), + GEN_INT (INTVAL (operands[2]) + 4))); + break; + case 2: + emit_insn (gen_vec_interleave_highv4sf (dest, operands[1], operands[1])); + break; + default: + /* 0 should be handled by the *vec_extractv4sf_0 pattern above. */ + gcc_unreachable (); + } + DONE; +} + [(set_attr "isa" "*,noavx,avx") + (set_attr "type" "sselog,*,*") + (set_attr "prefix_data16" "1,*,*") + (set_attr "prefix_extra" "1,*,*") + (set_attr "length_immediate" "1,*,*") + (set_attr "prefix" "maybe_vex,*,*") + (set_attr "mode" "V4SF,*,*")]) + +(define_insn_and_split "*vec_extract_v4sf_mem" + [(set (match_operand:SF 0 "register_operand" "=x,*r,f") + (vec_select:SF + (match_operand:V4SF 1 "memory_operand" "o,o,o") + (parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + int i = INTVAL (operands[2]); + + emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4)); + DONE; +}) + (define_expand "avx_vextractf128" [(match_operand: 0 "nonimmediate_operand" "") (match_operand:V_256 1 "register_operand" "") @@ -4044,62 +4100,6 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) -(define_insn_and_split "*sse4_1_extractps" - [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,x,x") - (vec_select:SF - (match_operand:V4SF 1 "register_operand" "x,0,x") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))] - "TARGET_SSE4_1" - "@ - %vextractps\t{%2, %1, %0|%0, %1, %2} - # - #" - "&& reload_completed && SSE_REG_P (operands[0])" - [(const_int 0)] -{ - rtx dest = gen_rtx_REG (V4SFmode, REGNO (operands[0])); - switch (INTVAL (operands[2])) - { - case 1: - case 3: - emit_insn (gen_sse_shufps_v4sf (dest, operands[1], operands[1], - operands[2], operands[2], - GEN_INT (INTVAL (operands[2]) + 4), - GEN_INT (INTVAL (operands[2]) + 4))); - break; - case 2: - emit_insn (gen_vec_interleave_highv4sf (dest, operands[1], operands[1])); - break; - default: - /* 0 should be handled by the *vec_extractv4sf_0 pattern above. */ - gcc_unreachable (); - } - DONE; -} - [(set_attr "isa" "*,noavx,avx") - (set_attr "type" "sselog,*,*") - (set_attr "prefix_data16" "1,*,*") - (set_attr "prefix_extra" "1,*,*") - (set_attr "length_immediate" "1,*,*") - (set_attr "prefix" "maybe_vex,*,*") - (set_attr "mode" "V4SF,*,*")]) - -(define_insn_and_split "*vec_extract_v4sf_mem" - [(set (match_operand:SF 0 "register_operand" "=x*rf") - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "o") - (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))] - "TARGET_SSE" - "#" - "&& reload_completed" - [(const_int 0)] -{ - int i = INTVAL (operands[2]); - - emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4)); - DONE; -}) - ;; Modes handled by vec_extract patterns. (define_mode_iterator VEC_EXTRACT_MODE [(V32QI "TARGET_AVX") V16QI