From: Alan Modra Date: Fri, 13 Sep 2002 05:22:59 +0000 (+0000) Subject: backport: PR c/7150, target/7380 X-Git-Tag: releases/gcc-3.2.1~285 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=42526a4a8f7ea5d9e3a2804c84dfc191c407ed12;p=thirdparty%2Fgcc.git backport: PR c/7150, target/7380 Merge from mainline. 2002-07-24 Alan Modra PR c/7150, target/7380 * config/rs6000/rs6000.md: Remove scratch reg on insns using addze and similar (plus (comparison r1 r2) r3) insns. Add missing scratch reg in one case. Formatting fixes. From-SVN: r57091 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d3d9caa2015..c2069e5edc11 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2002-09-13 Alan Modra + + Merge from mainline. + 2002-07-24 Alan Modra + PR c/7150, target/7380 + * config/rs6000/rs6000.md: Remove scratch reg on insns using + addze and similar (plus (comparison r1 r2) r3) insns. Add + missing scratch reg in one case. Formatting fixes. + 2002-09-13 Alan Modra * config/rs6000/rs6000.c (rs6000_emit_load_toc_table): Remove "if" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0587bd83894c..f032bfd81b8e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11253,15 +11253,14 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11292,46 +11291,43 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (le:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11481,37 +11477,34 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11525,14 +11518,13 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "! TARGET_POWERPC64" - "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -11562,34 +11554,32 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (leu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -11597,13 +11587,12 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + [(set (match_dup 0) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11648,13 +11637,12 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11683,44 +11671,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11815,46 +11800,43 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11905,21 +11887,20 @@ (clobber (match_scratch:SI 3 ""))] "TARGET_POWER && reload_completed" [(parallel [(set (match_dup 0) - (ge:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))]) + (ge:SI (match_dup 1) (match_dup 2))) + (clobber (match_dup 3))]) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11948,44 +11929,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12130,39 +12108,36 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 + {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 + {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,8,12,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12178,16 +12153,15 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -12219,36 +12193,34 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (geu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -12256,13 +12228,11 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12394,13 +12364,12 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:DI 2 "gpc_reg_operand" "r"))) - (clobber (match_scratch:DI 3 "=&r"))] + (match_operand:DI 2 "gpc_reg_operand" "r")))] "TARGET_POWERPC64" - "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" + "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" [(set_attr "length" "12")]) (define_insn "" @@ -12461,92 +12430,85 @@ "TARGET_POWERPC64 && reload_completed" [(set (match_dup 3) (plus:DI (gt:DI (match_dup 1) (const_int 0)) - (match_dup 2))) + (match_dup 2))) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64" "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 + {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 ""))] + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 "=&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64" "@ - addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 + addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 ""))] + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -12574,45 +12536,41 @@ (clobber (match_scratch:SI 4 ""))] "TARGET_POWER && reload_completed" [(set (match_dup 4) - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12731,15 +12689,14 @@ [(set_attr "length" "8,12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_short_operand" "I,rI")) - (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) - (clobber (match_scratch:DI 4 "=&r,&r"))] + (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" + addic %0,%1,%k2\;addze %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" [(set_attr "length" "8,12")]) (define_insn "" @@ -12770,7 +12727,7 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] @@ -12811,77 +12768,71 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze. %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 + addic %0,%1,%k2\;addze. %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_short_operand" "")) (match_operand:DI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 ""))] + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "")