From: Greg Kroah-Hartman Date: Wed, 30 Jul 2025 08:00:05 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v6.6.101~9 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=43762a008523480b8bbc5ac95743e6d900409e98;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: alsa-hda-add-missing-nvidia-hda-codec-ids.patch alsa-hda-tegra-add-tegra264-support.patch drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch --- diff --git a/queue-6.1/alsa-hda-add-missing-nvidia-hda-codec-ids.patch b/queue-6.1/alsa-hda-add-missing-nvidia-hda-codec-ids.patch new file mode 100644 index 0000000000..ae6be0722b --- /dev/null +++ b/queue-6.1/alsa-hda-add-missing-nvidia-hda-codec-ids.patch @@ -0,0 +1,67 @@ +From e0a911ac86857a73182edde9e50d9b4b949b7f01 Mon Sep 17 00:00:00 2001 +From: Daniel Dadap +Date: Thu, 26 Jun 2025 16:16:30 -0500 +Subject: ALSA: hda: Add missing NVIDIA HDA codec IDs + +From: Daniel Dadap + +commit e0a911ac86857a73182edde9e50d9b4b949b7f01 upstream. + +Add codec IDs for several NVIDIA products with HDA controllers to the +snd_hda_id_hdmi[] patch table. + +Signed-off-by: Daniel Dadap +Cc: +Link: https://patch.msgid.link/aF24rqwMKFWoHu12@ddadap-lakeline.nvidia.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_hdmi.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -4556,7 +4556,9 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HD + HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0033, "SoC 33 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0035, "SoC 35 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), +@@ -4595,15 +4597,32 @@ HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI + HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de009b, "GPU 9b HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de009c, "GPU 9c HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a1, "GPU a1 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a8, "GPU a8 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a9, "GPU a9 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00aa, "GPU aa HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ab, "GPU ab HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ad, "GPU ad HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ae, "GPU ae HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00af, "GPU af HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00b0, "GPU b0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00b1, "GPU b1 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c0, "GPU c0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c1, "GPU c1 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c3, "GPU c3 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c4, "GPU c4 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c5, "GPU c5 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), + HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), + HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi), diff --git a/queue-6.1/alsa-hda-tegra-add-tegra264-support.patch b/queue-6.1/alsa-hda-tegra-add-tegra264-support.patch new file mode 100644 index 0000000000..99a8859c71 --- /dev/null +++ b/queue-6.1/alsa-hda-tegra-add-tegra264-support.patch @@ -0,0 +1,161 @@ +From 1c4193917eb3279788968639f24d72ffeebdec6b Mon Sep 17 00:00:00 2001 +From: Mohan Kumar D +Date: Mon, 12 May 2025 06:42:58 +0000 +Subject: ALSA: hda/tegra: Add Tegra264 support + +From: Mohan Kumar D + +commit 1c4193917eb3279788968639f24d72ffeebdec6b upstream. + +Update HDA driver to support Tegra264 differences from legacy HDA, +which includes: clocks/resets, always power on, and hardware-managed +FPCI/IPFS initialization. The driver retrieves this chip-specific +information from soc_data. + +Signed-off-by: Mohan Kumar D +Signed-off-by: Sheetal +Signed-off-by: Takashi Iwai +Link: https://patch.msgid.link/20250512064258.1028331-4-sheetal@nvidia.com +Stable-dep-of: e0a911ac8685 ("ALSA: hda: Add missing NVIDIA HDA codec IDs") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/hda_tegra.c | 51 +++++++++++++++++++++++++++++++++++++++------ + sound/pci/hda/patch_hdmi.c | 1 + 2 files changed, 46 insertions(+), 6 deletions(-) + +--- a/sound/pci/hda/hda_tegra.c ++++ b/sound/pci/hda/hda_tegra.c +@@ -71,6 +71,10 @@ + struct hda_tegra_soc { + bool has_hda2codec_2x_reset; + bool has_hda2hdmi; ++ bool has_hda2codec_2x; ++ bool input_stream; ++ bool always_on; ++ bool requires_init; + }; + + struct hda_tegra { +@@ -186,7 +190,9 @@ static int __maybe_unused hda_tegra_runt + if (rc != 0) + return rc; + if (chip->running) { +- hda_tegra_init(hda); ++ if (hda->soc->requires_init) ++ hda_tegra_init(hda); ++ + azx_init_chip(chip, 1); + /* disable controller wake up event*/ + azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & +@@ -251,7 +257,8 @@ static int hda_tegra_init_chip(struct az + bus->remap_addr = hda->regs + HDA_BAR0; + bus->addr = res->start + HDA_BAR0; + +- hda_tegra_init(hda); ++ if (hda->soc->requires_init) ++ hda_tegra_init(hda); + + return 0; + } +@@ -324,7 +331,7 @@ static int hda_tegra_first_init(struct a + * starts with offset 0 which is wrong as HW register for output stream + * offset starts with 4. + */ +- if (of_device_is_compatible(np, "nvidia,tegra234-hda")) ++ if (!hda->soc->input_stream) + chip->capture_streams = 4; + + chip->playback_streams = (gcap >> 12) & 0x0f; +@@ -420,7 +427,6 @@ static int hda_tegra_create(struct snd_c + chip->driver_caps = driver_caps; + chip->driver_type = driver_caps & 0xff; + chip->dev_index = 0; +- chip->jackpoll_interval = msecs_to_jiffies(5000); + INIT_LIST_HEAD(&chip->pcm_list); + + chip->codec_probe_mask = -1; +@@ -437,7 +443,16 @@ static int hda_tegra_create(struct snd_c + chip->bus.core.sync_write = 0; + chip->bus.core.needs_damn_long_delay = 1; + chip->bus.core.aligned_mmio = 1; +- chip->bus.jackpoll_in_suspend = 1; ++ ++ /* ++ * HDA power domain and clocks are always on for Tegra264 and ++ * the jack detection logic would work always, so no need of ++ * jack polling mechanism running. ++ */ ++ if (!hda->soc->always_on) { ++ chip->jackpoll_interval = msecs_to_jiffies(5000); ++ chip->bus.jackpoll_in_suspend = 1; ++ } + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); + if (err < 0) { +@@ -451,22 +466,44 @@ static int hda_tegra_create(struct snd_c + static const struct hda_tegra_soc tegra30_data = { + .has_hda2codec_2x_reset = true, + .has_hda2hdmi = true, ++ .has_hda2codec_2x = true, ++ .input_stream = true, ++ .always_on = false, ++ .requires_init = true, + }; + + static const struct hda_tegra_soc tegra194_data = { + .has_hda2codec_2x_reset = false, + .has_hda2hdmi = true, ++ .has_hda2codec_2x = true, ++ .input_stream = true, ++ .always_on = false, ++ .requires_init = true, + }; + + static const struct hda_tegra_soc tegra234_data = { + .has_hda2codec_2x_reset = true, + .has_hda2hdmi = false, ++ .has_hda2codec_2x = true, ++ .input_stream = false, ++ .always_on = false, ++ .requires_init = true, ++}; ++ ++static const struct hda_tegra_soc tegra264_data = { ++ .has_hda2codec_2x_reset = true, ++ .has_hda2hdmi = false, ++ .has_hda2codec_2x = false, ++ .input_stream = false, ++ .always_on = true, ++ .requires_init = false, + }; + + static const struct of_device_id hda_tegra_match[] = { + { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data }, + { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data }, + { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data }, ++ { .compatible = "nvidia,tegra264-hda", .data = &tegra264_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, hda_tegra_match); +@@ -521,7 +558,9 @@ static int hda_tegra_probe(struct platfo + hda->clocks[hda->nclocks++].id = "hda"; + if (hda->soc->has_hda2hdmi) + hda->clocks[hda->nclocks++].id = "hda2hdmi"; +- hda->clocks[hda->nclocks++].id = "hda2codec_2x"; ++ ++ if (hda->soc->has_hda2codec_2x) ++ hda->clocks[hda->nclocks++].id = "hda2codec_2x"; + + err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); + if (err < 0) +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -4556,6 +4556,7 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HD + HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), diff --git a/queue-6.1/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch b/queue-6.1/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch new file mode 100644 index 0000000000..498c7cf6ea --- /dev/null +++ b/queue-6.1/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch @@ -0,0 +1,59 @@ +From 9e0c433d0c05fde284025264b89eaa4ad59f0a3e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 10 Jul 2025 23:17:12 +0300 +Subject: drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 9e0c433d0c05fde284025264b89eaa4ad59f0a3e upstream. + +On g4x we currently use the 96MHz non-SSC refclk, which can't actually +generate an exact 2.7 Gbps link rate. In practice we end up with 2.688 +Gbps which seems to be close enough to actually work, but link training +is currently failing due to miscalculating the DP_LINK_BW value (we +calcualte it directly from port_clock which reflects the actual PLL +outpout frequency). + +Ideas how to fix this: +- nudge port_clock back up to 270000 during PLL computation/readout +- track port_clock and the nominal link rate separately so they might + differ a bit +- switch to the 100MHz refclk, but that one should be SSC so perhaps + not something we want + +While we ponder about a better solution apply some band aid to the +immediate issue of miscalculated DP_LINK_BW value. With this +I can again use 2.7 Gbps link rate on g4x. + +Cc: stable@vger.kernel.org +Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state") +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20250710201718.25310-2-ville.syrjala@linux.intel.com +Reviewed-by: Imre Deak +(cherry picked from commit a8b874694db5cae7baaf522756f87acd956e6e66) +Signed-off-by: Rodrigo Vivi +[ changed display->platform.g4x to IS_G4X(i915) ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -1139,6 +1139,12 @@ int intel_dp_rate_select(struct intel_dp + void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, + u8 *link_bw, u8 *rate_select) + { ++ struct drm_i915_private *i915 = dp_to_i915(intel_dp); ++ ++ /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */ ++ if (IS_G4X(i915) && port_clock == 268800) ++ port_clock = 270000; ++ + /* eDP 1.4 rate select method. */ + if (intel_dp->use_rate_select) { + *link_bw = 0; diff --git a/queue-6.1/series b/queue-6.1/series index 577901c7ec..e98257acb9 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -47,3 +47,6 @@ usb-typec-tcpm-apply-vbus-before-data-bringup-in-tcpm_src_attach.patch x86-bugs-fix-use-of-possibly-uninit-value-in-amd_check_tsa_microcode.patch jfs-reject-on-disk-inodes-of-an-unsupported-type.patch comedi-comedi_test-fix-possible-deletion-of-uninitialized-timers.patch +alsa-hda-tegra-add-tegra264-support.patch +alsa-hda-add-missing-nvidia-hda-codec-ids.patch +drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch