From: Neil Horman <nhorman@openssl.org>
Date: Wed, 31 Dec 2025 21:38:21 +0000 (-0500)
Subject: Fix register save/restore issue in ppc
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=441a2c105c7074502b0dc4ccd4aa2ed11d305556;p=thirdparty%2Fopenssl.git

Fix register save/restore issue in ppc

Recently, the addition of some vector register save restore logic from:
https://github.com/openssl/openssl/pull/28990

Triggered an issue in our quic_multistream_test, notably causing a
connection shutdown with error code 1, rather than successful
completion.

The problem has been root caused to an error in how the ppc aes code
saves and restores vector registers.

The aes gcm code uses VSR instructions (vsldoi, etc), to maniuplate
vector registers, which only operate on the upper half of the vector
register file (VS32-63), and operands are implicitly offset to do this.
(i.e. <instr> v31 actually operates on register vs63).

However, the SAVE/RESTORE macros which save and restore those values use
stxv/lxv instructions to do the save and restore, which are VSX
instructions that have access to the full vector register file, and so
by restoring V1, rather than V33, etc, we actuall restore values to the
wrong registers, causing various issues (most notably the above
misconfiguration of the quic SSL shutdown event, which sets the error
code erroneously to 1 instead of the expected 0 value).

Fix it by offsetting the SAVE_REGS and RESTORE_REGS macros to reference
the proper registers when doing save and restore.

Fixes #29516

Reviewed-by: Saša Nedvědický <sashan@openssl.org>
Reviewed-by: Tim Hudson <tjh@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/29528)
---

diff --git a/crypto/modes/asm/aes-gcm-ppc.pl b/crypto/modes/asm/aes-gcm-ppc.pl
index 99f82bf8b8b..68918a9305a 100644
--- a/crypto/modes/asm/aes-gcm-ppc.pl
+++ b/crypto/modes/asm/aes-gcm-ppc.pl
@@ -73,33 +73,33 @@ my $code.=<<___;
 	std	23, 184(1)
 	std	24, 192(1)
 
-	stxv	20, 256(1)
-	stxv	21, 256+16(1)
-	stxv	22, 256+32(1)
-	stxv	23, 256+48(1)
-	stxv	24, 256+64(1)
-	stxv	25, 256+80(1)
-	stxv	26, 256+96(1)
-	stxv	27, 256+112(1)
-	stxv	28, 256+128(1)
-	stxv	29, 256+144(1)
-	stxv	30, 256+160(1)
-	stxv	31, 256+176(1)
+	stxv	32+20, 256(1)
+	stxv	32+21, 256+16(1)
+	stxv	32+22, 256+32(1)
+	stxv	32+23, 256+48(1)
+	stxv	32+24, 256+64(1)
+	stxv	32+25, 256+80(1)
+	stxv	32+26, 256+96(1)
+	stxv	32+27, 256+112(1)
+	stxv	32+28, 256+128(1)
+	stxv	32+29, 256+144(1)
+	stxv	32+30, 256+160(1)
+	stxv	32+31, 256+176(1)
 .endm # SAVE_REGS
 
 .macro RESTORE_REGS
-	lxv	20, 256(1)
-	lxv	21, 256+16(1)
-	lxv	22, 256+32(1)
-	lxv	23, 256+48(1)
-	lxv	24, 256+64(1)
-	lxv	25, 256+80(1)
-	lxv	26, 256+96(1)
-	lxv	27, 256+112(1)
-	lxv	28, 256+128(1)
-	lxv	29, 256+144(1)
-	lxv	30, 256+160(1)
-	lxv	31, 256+176(1)
+	lxv	32+20, 256(1)
+	lxv	32+21, 256+16(1)
+	lxv	32+22, 256+32(1)
+	lxv	32+23, 256+48(1)
+	lxv	32+24, 256+64(1)
+	lxv	32+25, 256+80(1)
+	lxv	32+26, 256+96(1)
+	lxv	32+27, 256+112(1)
+	lxv	32+28, 256+128(1)
+	lxv	32+29, 256+144(1)
+	lxv	32+30, 256+160(1)
+	lxv	32+31, 256+176(1)
 
 	ld	14, 112(1)
 	ld	15, 120(1)