From: Karl Meakin <karl.meakin@arm.com>
Date: Thu, 18 Sep 2025 14:15:45 +0000 (+0100)
Subject: AArch64: Add SME LUTv2 architecture extension
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=45ddf553534e2235545e0e9019dfe3d58eb25612;p=thirdparty%2Fgcc.git

AArch64: Add SME LUTv2 architecture extension

Add the SME LUTv2 architecture extension. Users can enable the extension
by adding `+sme-lutv2` to `-march` or `-mcpu`, and test for its presence
with the `__ARM_FEATURE_SME_LUTv2` macro. The intrinsics will be added
in the next commit.

gcc/ChangeLog:

	* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Conditonally define
	`__ARM_FEATURE_SME_LUTv2" macro.
	* config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION("sme-lutv2")): New
	optional architecture extension.
	* config/aarch64/aarch64.h (TARGET_SME_LUTv2): New macro.
	* doc/invoke.texi: Document `+sme-lutv2` flag.
---

diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 98337b7f693..a8ff58e4994 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -269,6 +269,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
 			"__ARM_FEATURE_SVE_BF16", pfile);
 
   aarch64_def_or_undef (TARGET_LUT, "__ARM_FEATURE_LUT", pfile);
+  aarch64_def_or_undef (TARGET_SME_LUTv2, "__ARM_FEATURE_SME_LUTv2", pfile);
 
   aarch64_def_or_undef (TARGET_FP8, "__ARM_FEATURE_FP8", pfile);
 
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index db88df08a6a..a70375c053f 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -277,6 +277,8 @@ AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2, (SME2, FP8), (), (), "smesf8
 
 AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
 
+AARCH64_OPT_EXTENSION ("sme-lutv2", SME_LUTv2, (SME2), (), (), "sme-lutv2")
+
 AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
 
 #undef AARCH64_OPT_FMV_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 2b3610c86ed..2b6075d3824 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -477,9 +477,14 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
    enabled through +faminmax.  */
 #define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX)
 
-/* Lookup table (LUTI) extension instructions are enabled through +lut.  */
+/* Lookup table (LUTI) extension instructions with 2-bit and 4-bit indices are
+   enabled through +lut.  */
 #define TARGET_LUT AARCH64_HAVE_ISA (LUT)
 
+/* Lookup table (LUTI) extension instructions with 4-bit indices and 8-bit
+   elements are enabled through +sme-lutv2.  */
+#define TARGET_SME_LUTv2 AARCH64_HAVE_ISA (SME_LUTv2)
+
 /* Prefer different predicate registers for the output of a predicated
    operation over re-using an existing input predicate.  */
 #define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3cf326cc22c..76ecea550f3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22728,6 +22728,8 @@ extension in streaming mode.
 Enable the Floating Point Absolute Maximum/Minimum extension.
 @item lut
 Enable the Lookup Table extension.
+@item sme-lutv2
+Enable the SME Lookup Table v2 (LUTv2) extension.
 @item cpa
 Enable the Checked Pointer Arithmetic instructions.
 @item sve-b16b16