From: Shiji Yang Date: Mon, 19 Jan 2026 14:26:09 +0000 (+0800) Subject: mediatek: dts: mt7981: fix spi clocks X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=46129bbbf5a423fd44a21b2f80f27a5a579fbb56;p=thirdparty%2Fopenwrt.git mediatek: dts: mt7981: fix spi clocks Fix spi1 sel-clk source and add missing assigned-clocks. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/21108 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch b/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch new file mode 100644 index 00000000000..d75f7dd12f8 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch @@ -0,0 +1,53 @@ +From 0c74ae06ed6b6c9627712a74ecee4e61bbd4092d Mon Sep 17 00:00:00 2001 +From: developer +Date: Mon, 19 Jan 2026 21:42:29 +0800 +Subject: [PATCH] arm64: dts: mediatek: fix mt7981 spim clock + +1) Add spi0/1/2 clock parent setting +2) Fix spi1 clock_sel to CLK_TOP_SPIM_MST_SEL + +Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/836034ca0baad57e4c287a62ccc5677c60be0e18 +Signed-off-by: Shiji Yang +--- + arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +@@ -248,6 +248,10 @@ + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2_CK>, + <&infracfg CLK_INFRA_SPI2_HCK_CK>; ++ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_SPI2_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; +@@ -262,6 +266,10 @@ + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; ++ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_SPI0_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; +@@ -273,9 +281,13 @@ + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, +- <&topckgen CLK_TOP_SPI_SEL>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; ++ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, ++ <&infracfg CLK_INFRA_SPI1_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>;