From: Ian Bolton Date: Tue, 22 Apr 2014 09:33:00 +0000 (+0000) Subject: arm-protos.h (tune_params): New struct members. X-Git-Tag: releases/gcc-5.1.0~8019 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=46fbb3ebaee00772935fff931e2edf31f10306e4;p=thirdparty%2Fgcc.git arm-protos.h (tune_params): New struct members. * config/arm/arm-protos.h (tune_params): New struct members. * config/arm/arm.c: Initialise tune_params per processor. (thumb2_reorg): Suppress conversion from t32 to t16 when optimizing for speed, based on new tune_params. From-SVN: r209561 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4eab80869f5f..e34c39fde464 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2014-04-22 Ian Bolton + + * config/arm/arm-protos.h (tune_params): New struct members. + * config/arm/arm.c: Initialise tune_params per processor. + (thumb2_reorg): Suppress conversion from t32 to t16 when optimizing + for speed, based on new tune_params. + 2014-04-22 Alex Velenko * config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 13874ee6e50a..74645ee1d245 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -272,6 +272,11 @@ struct tune_params const struct cpu_vec_costs* vec_costs; /* Prefer Neon for 64-bit bitops. */ bool prefer_neon_for_64bits; + /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ + bool disparage_flag_setting_t16_encodings; + /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags + would be set. */ + bool disparage_partial_flag_setting_t16_encodings; }; extern const struct tune_params *current_tune; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 822060dd2f32..08b52557586c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1484,7 +1484,8 @@ const struct tune_params arm_slowmul_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_fastmul_tune = @@ -1500,7 +1501,8 @@ const struct tune_params arm_fastmul_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -1519,7 +1521,8 @@ const struct tune_params arm_strongarm_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_xscale_tune = @@ -1535,7 +1538,8 @@ const struct tune_params arm_xscale_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_9e_tune = @@ -1551,7 +1555,8 @@ const struct tune_params arm_9e_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_v6t2_tune = @@ -1567,7 +1572,8 @@ const struct tune_params arm_v6t2_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -1584,7 +1590,8 @@ const struct tune_params arm_cortex_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a7_tune = @@ -1600,7 +1607,8 @@ const struct tune_params arm_cortex_a7_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a15_tune = @@ -1616,7 +1624,8 @@ const struct tune_params arm_cortex_a15_tune = true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + true, true /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a53_tune = @@ -1632,7 +1641,8 @@ const struct tune_params arm_cortex_a53_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a57_tune = @@ -1667,7 +1677,8 @@ const struct tune_params arm_cortex_a5_tune = false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a9_tune = @@ -1683,7 +1694,8 @@ const struct tune_params arm_cortex_a9_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_cortex_a12_tune = @@ -1722,7 +1734,8 @@ const struct tune_params arm_v7m_tune = false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than @@ -1740,7 +1753,8 @@ const struct tune_params arm_v6m_tune = false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; const struct tune_params arm_fa726te_tune = @@ -1756,7 +1770,8 @@ const struct tune_params arm_fa726te_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; @@ -16793,9 +16808,20 @@ thumb2_reorg (void) compute_bb_for_insn (); df_analyze (); + enum Convert_Action {SKIP, CONV, SWAP_CONV}; + FOR_EACH_BB_FN (bb, cfun) { + if (current_tune->disparage_flag_setting_t16_encodings + && optimize_bb_for_speed_p (bb)) + continue; + rtx insn; + Convert_Action action = SKIP; + Convert_Action action_for_partial_flag_setting + = (current_tune->disparage_partial_flag_setting_t16_encodings + && optimize_bb_for_speed_p (bb)) + ? SKIP : CONV; COPY_REG_SET (&live, DF_LR_OUT (bb)); df_simulate_initialize_backwards (bb, &live); @@ -16805,7 +16831,7 @@ thumb2_reorg (void) && !REGNO_REG_SET_P (&live, CC_REGNUM) && GET_CODE (PATTERN (insn)) == SET) { - enum {SKIP, CONV, SWAP_CONV} action = SKIP; + action = SKIP; rtx pat = PATTERN (insn); rtx dst = XEXP (pat, 0); rtx src = XEXP (pat, 1); @@ -16886,10 +16912,11 @@ thumb2_reorg (void) /* ANDS , */ if (rtx_equal_p (dst, op0) && low_register_operand (op1, SImode)) - action = CONV; + action = action_for_partial_flag_setting; else if (rtx_equal_p (dst, op1) && low_register_operand (op0, SImode)) - action = SWAP_CONV; + action = action_for_partial_flag_setting == SKIP + ? SKIP : SWAP_CONV; break; case ASHIFTRT: @@ -16900,26 +16927,30 @@ thumb2_reorg (void) /* LSLS , */ if (rtx_equal_p (dst, op0) && low_register_operand (op1, SImode)) - action = CONV; + action = action_for_partial_flag_setting; /* ASRS ,,# */ /* LSRS ,,# */ /* LSLS ,,# */ else if (low_register_operand (op0, SImode) && CONST_INT_P (op1) && IN_RANGE (INTVAL (op1), 0, 31)) - action = CONV; + action = action_for_partial_flag_setting; break; case ROTATERT: /* RORS , */ if (rtx_equal_p (dst, op0) && low_register_operand (op1, SImode)) - action = CONV; + action = action_for_partial_flag_setting; break; case NOT: - case NEG: /* MVNS , */ + if (low_register_operand (op0, SImode)) + action = action_for_partial_flag_setting; + break; + + case NEG: /* NEGS , (a.k.a RSBS) */ if (low_register_operand (op0, SImode)) action = CONV; @@ -16929,7 +16960,7 @@ thumb2_reorg (void) /* MOVS ,# */ if (CONST_INT_P (src) && IN_RANGE (INTVAL (src), 0, 255)) - action = CONV; + action = action_for_partial_flag_setting; break; case REG: