From: Cerion Armour-Brown Date: Thu, 17 Mar 2005 14:03:36 +0000 (+0000) Subject: Quieten down gcc X-Git-Tag: svn/VALGRIND_3_0_1^2~282 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4716af94df82d17c12dcbb1d6c955191488ab19f;p=thirdparty%2Fvalgrind.git Quieten down gcc git-svn-id: svn://svn.valgrind.org/vex/trunk@1052 --- diff --git a/VEX/priv/guest-amd64/ghelpers.c b/VEX/priv/guest-amd64/ghelpers.c index 80d8e74413..995a0035c2 100644 --- a/VEX/priv/guest-amd64/ghelpers.c +++ b/VEX/priv/guest-amd64/ghelpers.c @@ -92,6 +92,7 @@ static void mullS64 ( Long u, Long v, Long* rHi, Long* rLo ) *rLo = u * v; } +#if 0 /* UNUSED */ static void mullU64 ( ULong u, ULong v, ULong* rHi, ULong* rLo ) { ULong u0, v0, w0; @@ -108,6 +109,7 @@ static void mullU64 ( ULong u, ULong v, ULong* rHi, ULong* rLo ) *rHi = u1 * v1 + w2 + (w1 >> 32); *rLo = u * v; } +#endif /* UNUSED */ static const UChar parity_table[256] = { diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c index f76ee1b353..607c838d4a 100644 --- a/VEX/priv/guest-amd64/toIR.c +++ b/VEX/priv/guest-amd64/toIR.c @@ -3273,29 +3273,31 @@ ULong dis_Grp2 ( Prefix pfx, //.. //-- Addr eip, UChar modrm, //.. //-- Int am_sz, Int sz, UInt src_val ) //.. //-- { -//.. # define MODIFY_t2_AND_SET_CARRY_FLAG \ -//.. /* t2 is the value to be op'd on. Copy to t_fetched, then \ -//.. modify t2, if non-BT. */ \ -//.. uInstr2(cb, MOV, 4, TempReg, t2, TempReg, t_fetched); \ -//.. uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \ -//.. uLiteral(cb, v_mask); \ -//.. switch (gregOfRM(modrm)) { \ -//.. case 4: /* BT */ break; \ -//.. case 5: /* BTS */ \ -//.. uInstr2(cb, OR, sz, TempReg, t_mask, TempReg, t2); break; \ -//.. case 6: /* BTR */ \ -//.. uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t2); break; \ -//.. case 7: /* BTC */ \ -//.. uInstr2(cb, XOR, sz, TempReg, t_mask, TempReg, t2); break; \ -//.. } \ -//.. /* Copy relevant bit from t_fetched into carry flag. */ \ -//.. uInstr2(cb, SHR, sz, Literal, 0, TempReg, t_fetched); \ -//.. uLiteral(cb, src_val); \ -//.. uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \ -//.. uLiteral(cb, 1); \ -//.. uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t_fetched); \ -//.. uInstr1(cb, NEG, sz, TempReg, t_fetched); \ -//.. setFlagsFromUOpcode(cb, NEG); +#if 0 /* stop gcc multi-line comment warning */ +/.. # define MODIFY_t2_AND_SET_CARRY_FLAG \ +/.. /* t2 is the value to be op'd on. Copy to t_fetched, then \ +/.. modify t2, if non-BT. */ \ +/.. uInstr2(cb, MOV, 4, TempReg, t2, TempReg, t_fetched); \ +/.. uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \ +/.. uLiteral(cb, v_mask); \ +/.. switch (gregOfRM(modrm)) { \ +/.. case 4: /* BT */ break; \ +/.. case 5: /* BTS */ \ +/.. uInstr2(cb, OR, sz, TempReg, t_mask, TempReg, t2); break; \ +/.. case 6: /* BTR */ \ +/.. uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t2); break; \ +/.. case 7: /* BTC */ \ +/.. uInstr2(cb, XOR, sz, TempReg, t_mask, TempReg, t2); break; \ +/.. } \ +/.. /* Copy relevant bit from t_fetched into carry flag. */ \ +/.. uInstr2(cb, SHR, sz, Literal, 0, TempReg, t_fetched); \ +/.. uLiteral(cb, src_val); \ +/.. uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \ +/.. uLiteral(cb, 1); \ +/.. uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t_fetched); \ +/.. uInstr1(cb, NEG, sz, TempReg, t_fetched); \ +/.. setFlagsFromUOpcode(cb, NEG); +#endif /* stop gcc multi-line comment warning */ //.. //.. //-- /* src_val denotes a d8. @@ -6309,9 +6311,11 @@ ULong dis_FPU ( Bool* decode_ok, Prefix pfx, ULong delta ) //.. delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pxor", False ); //.. break; //.. -//.. # define SHIFT_BY_REG(_name,_op) \ -//.. delta = dis_MMX_shiftG_byE(sorb, delta, _name, _op); \ -//.. break; +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SHIFT_BY_REG(_name,_op) \ +/.. delta = dis_MMX_shiftG_byE(sorb, delta, _name, _op); \ +/.. break; +#endif /* stop gcc multi-line comment warning */ //.. //.. /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */ //.. case 0xF1: SHIFT_BY_REG("psllw", Iop_ShlN16x4); @@ -6342,9 +6346,11 @@ ULong dis_FPU ( Bool* decode_ok, Prefix pfx, ULong delta ) //.. byte2 = getUChar(delta); /* amode / sub-opcode */ //.. subopc = (byte2 >> 3) & 7; //.. -//.. # define SHIFT_BY_IMM(_name,_op) \ -//.. do { delta = dis_MMX_shiftE_imm(delta,_name,_op); \ -//.. } while (0) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SHIFT_BY_IMM(_name,_op) \ +/.. do { delta = dis_MMX_shiftE_imm(delta,_name,_op); \ +/.. } while (0) +#endif /* stop gcc multi-line comment warning */ //.. //.. hAddr = NULL; //.. hName = NULL; @@ -8953,8 +8959,10 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. } //.. breakup64to16s( sV, &s3, &s2, &s1, &s0 ); //.. -//.. # define SEL(n) \ -//.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SEL(n) \ +/.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#endif /* stop gcc multi-line comment warning */ //.. assign(dV, //.. mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), //.. SEL((order>>2)&3), SEL((order>>0)&3) ) @@ -9303,9 +9311,11 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( rmode, get_sse_roundingmode() ); //.. breakup128to32s( argV, &t3, &t2, &t1, &t0 ); //.. -//.. # define CVT(_t) binop( Iop_F64toF32, \ -//.. mkexpr(rmode), \ -//.. unop(Iop_I32toF64,mkexpr(_t))) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) binop( Iop_F64toF32, \ +/.. mkexpr(rmode), \ +/.. unop(Iop_I32toF64,mkexpr(_t))) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); //.. putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); @@ -9346,9 +9356,11 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( t1, unop(Iop_ReinterpI64asF64, //.. unop(Iop_128HIto64, mkexpr(argV))) ); //.. -//.. # define CVT(_t) binop( Iop_F64toI32, \ -//.. mkexpr(rmode), \ -//.. mkexpr(_t) ) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) binop( Iop_F64toI32, \ +/.. mkexpr(rmode), \ +/.. mkexpr(_t) ) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); //.. putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); @@ -9442,9 +9454,11 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( t1, unop(Iop_ReinterpI64asF64, //.. unop(Iop_128HIto64, mkexpr(argV))) ); //.. -//.. # define CVT(_t) binop( Iop_F64toF32, \ -//.. mkexpr(rmode), \ -//.. mkexpr(_t) ) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) binop( Iop_F64toF32, \ +/.. mkexpr(rmode), \ +/.. mkexpr(_t) ) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); //.. putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); @@ -9514,11 +9528,13 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. //.. /* This is less than ideal. If it turns out to be a performance //.. bottleneck it can be improved. */ -//.. # define CVT(_t) \ -//.. binop( Iop_F64toI32, \ -//.. mkexpr(rmode), \ -//.. unop( Iop_F32toF64, \ -//.. unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) \ +/.. binop( Iop_F64toI32, \ +/.. mkexpr(rmode), \ +/.. unop( Iop_F32toF64, \ +/.. unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); //.. putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); @@ -9750,9 +9766,11 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( t1, unop(Iop_ReinterpI64asF64, //.. unop(Iop_128HIto64, mkexpr(argV))) ); //.. -//.. # define CVT(_t) binop( Iop_F64toI32, \ -//.. mkexpr(rmode), \ -//.. mkexpr(_t) ) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) binop( Iop_F64toI32, \ +/.. mkexpr(rmode), \ +/.. mkexpr(_t) ) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); //.. putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); @@ -9790,11 +9808,13 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. //.. /* This is less than ideal. If it turns out to be a performance //.. bottleneck it can be improved. */ -//.. # define CVT(_t) \ -//.. binop( Iop_F64toI32, \ -//.. mkexpr(rmode), \ -//.. unop( Iop_F32toF64, \ -//.. unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define CVT(_t) \ +/.. binop( Iop_F64toI32, \ +/.. mkexpr(rmode), \ +/.. unop( Iop_F32toF64, \ +/.. unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) +#endif /* stop gcc multi-line comment warning */ //.. //.. putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); //.. putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); @@ -10764,8 +10784,10 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. } //.. breakup128to32s( sV, &s3, &s2, &s1, &s0 ); //.. -//.. # define SEL(n) \ -//.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SEL(n) \ +/.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#endif /* stop gcc multi-line comment warning */ //.. assign(dV, //.. mk128from32s( SEL((order>>6)&3), SEL((order>>4)&3), //.. SEL((order>>2)&3), SEL((order>>0)&3) ) @@ -10805,8 +10827,10 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( sVhi, unop(Iop_128HIto64, mkexpr(sV)) ); //.. breakup64to16s( sVhi, &s3, &s2, &s1, &s0 ); //.. -//.. # define SEL(n) \ -//.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SEL(n) \ +/.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#endif /* stop gcc multi-line comment warning */ //.. assign(dVhi, //.. mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), //.. SEL((order>>2)&3), SEL((order>>0)&3) ) @@ -10849,8 +10873,10 @@ DisResult disInstr ( /*IN*/ Bool resteerOK, //.. assign( sVlo, unop(Iop_128to64, mkexpr(sV)) ); //.. breakup64to16s( sVlo, &s3, &s2, &s1, &s0 ); //.. -//.. # define SEL(n) \ -//.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#if 0 /* stop gcc multi-line comment warning */ +/.. # define SEL(n) \ +/.. ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) +#endif /* stop gcc multi-line comment warning */ //.. assign(dVlo, //.. mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), //.. SEL((order>>2)&3), SEL((order>>0)&3) ) diff --git a/VEX/test_main.c b/VEX/test_main.c index 3638463109..126442a1a2 100644 --- a/VEX/test_main.c +++ b/VEX/test_main.c @@ -48,8 +48,10 @@ static UChar transbuf[N_TRANSBUF]; static Bool verbose = True; /* Forwards */ +#if 0 /* UNUSED */ static IRBB* ac_instrument ( IRBB*, VexGuestLayout*, IRType ); static IRBB* mc_instrument ( IRBB*, VexGuestLayout*, IRType ); +#endif static Bool chase_into_not_ok ( Addr64 dst ) { return False; } @@ -123,6 +125,10 @@ int main ( int argc, char** argv ) for (i = 0; i < TEST_N_ITERS; i++) tres = LibVEX_Translate ( +#if 0 /* ppc32 -> ppc32 */ + VexArchPPC32, VexSubArchPPC32_noAV, + VexArchPPC32, VexSubArchPPC32_noAV, +#endif #if 0 /* ppc32 -> x86 */ VexArchPPC32, VexSubArchPPC32_noAV, VexArchX86, VexSubArchX86_sse2, @@ -194,6 +200,7 @@ void panic ( Char* s ) failure_exit(); } +#if 0 /* UNUSED */ static IRBB* ac_instrument (IRBB* bb_in, VexGuestLayout* layout, IRType hWordTy ) { @@ -330,6 +337,7 @@ IRBB* ac_instrument (IRBB* bb_in, VexGuestLayout* layout, IRType hWordTy ) return bb; } +#endif /* UNUSED */ ////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// @@ -346,6 +354,21 @@ IRBB* ac_instrument (IRBB* bb_in, VexGuestLayout* layout, IRType hWordTy ) #define MC_(zzzz) MC_##zzzz #define TL_(zzzz) SK_##zzzz +#if 1 /* stop gcc complaining */ +void MC_helperc_complain_undef ( void ); +void MC_helperc_LOADV8 ( void ); +void MC_helperc_LOADV4 ( void ); +void MC_helperc_LOADV2 ( void ); +void MC_helperc_LOADV1 ( void ); +void MC_helperc_STOREV8( void ); +void MC_helperc_STOREV4( void ); +void MC_helperc_STOREV2( void ); +void MC_helperc_STOREV1( void ); +void MC_helperc_value_check0_fail( void ); +void MC_helperc_value_check1_fail( void ); +void MC_helperc_value_check4_fail( void ); +#endif + void MC_helperc_complain_undef ( void ) { } void MC_helperc_LOADV8 ( void ) { } void MC_helperc_LOADV4 ( void ) { } @@ -1017,6 +1040,7 @@ static Bool isAlwaysDefd ( MCEnv* mce, Int offset, Int size ) } +#if 0 /* UNUSED */ /* Generate into bb suitable actions to shadow this Put. If the state slice is marked 'always defined', do nothing. Otherwise, write the supplied V bits to the shadow state. We can pass in either an @@ -1083,6 +1107,7 @@ void do_shadow_PUTI ( MCEnv* mce, stmt( mce->bb, IRStmt_PutI( new_descr, ix, bias, vatom )); } } +#endif /* UNUSED */ /* Return an expression which contains the V bits corresponding to the @@ -1184,6 +1209,7 @@ IRAtom* mkLazyN ( MCEnv* mce, } +#if 0 /* UNUSED */ /*------------------------------------------------------------*/ /*--- Generating expensive sequences for exact carry-chain ---*/ /*--- propagation in add/sub and related operations. ---*/ @@ -1240,6 +1266,7 @@ IRAtom* expensiveAdd32 ( MCEnv* mce, IRAtom* qaa, IRAtom* qbb, ) ); } +#endif /* UNUSED */ /*------------------------------------------------------------*/ @@ -2050,6 +2077,7 @@ IRExpr* expr2vbits ( MCEnv* mce, IRExpr* e ) } } +#if 0 /* UNUSED */ /*------------------------------------------------------------*/ /*--- Generate shadow stmts from all kinds of IRStmts. ---*/ /*------------------------------------------------------------*/ @@ -2381,6 +2409,7 @@ void do_shadow_Dirty ( MCEnv* mce, IRDirty* d ) } } +#endif /* UNUSED */ /*------------------------------------------------------------*/ @@ -2457,6 +2486,7 @@ static Bool checkForBogusLiterals ( /*FLAT*/ IRStmt* st ) #endif /* UNUSED */ +#if 0 /* UNUSED */ IRBB* mc_instrument ( IRBB* bb_in, VexGuestLayout* layout, IRType hWordTy ) { Bool verboze = False; //True; @@ -2588,6 +2618,7 @@ IRBB* mc_instrument ( IRBB* bb_in, VexGuestLayout* layout, IRType hWordTy ) return bb; } +#endif /* UNUSED */ /*--------------------------------------------------------------------*/ /*--- end mc_translate.c ---*/