From: George Guo Date: Tue, 10 Feb 2026 11:31:06 +0000 (+0800) Subject: LoongArch: Add detection for SC.Q support X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=48543c4283e76d561d11b9955222b1a3054abdb9;p=thirdparty%2Fkernel%2Fstable.git LoongArch: Add detection for SC.Q support Check the CPUCFG2_SCQ bit to determine if the current CPU supports the SC.Q instruction. Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Signed-off-by: George Guo Signed-off-by: Huacai Chen --- diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h index 3745d991a99a9..8eefe7a2098b9 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -35,6 +35,7 @@ */ #define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG) #define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) #define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL) #define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU) #define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX) diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h index f3efb00b61414..1e60ab264cd08 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -95,39 +95,41 @@ static inline char *id_to_core_name(unsigned int id) */ #define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */ #define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */ -#define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */ -#define CPU_FEATURE_FPU 3 /* CPU has FPU */ -#define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */ -#define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */ -#define CPU_FEATURE_CRC32 6 /* CPU has CRC32 instructions */ -#define CPU_FEATURE_COMPLEX 7 /* CPU has Complex instructions */ -#define CPU_FEATURE_CRYPTO 8 /* CPU has Crypto instructions */ -#define CPU_FEATURE_LVZ 9 /* CPU has Virtualization extension */ -#define CPU_FEATURE_LBT_X86 10 /* CPU has X86 Binary Translation */ -#define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */ -#define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */ -#define CPU_FEATURE_TLB 13 /* CPU has TLB */ -#define CPU_FEATURE_CSR 14 /* CPU has CSR */ -#define CPU_FEATURE_IOCSR 15 /* CPU has IOCSR */ -#define CPU_FEATURE_WATCH 16 /* CPU has watchpoint registers */ -#define CPU_FEATURE_VINT 17 /* CPU has vectored interrupts */ -#define CPU_FEATURE_CSRIPI 18 /* CPU has CSR-IPI */ -#define CPU_FEATURE_EXTIOI 19 /* CPU has EXT-IOI */ -#define CPU_FEATURE_PREFETCH 20 /* CPU has prefetch instructions */ -#define CPU_FEATURE_PMP 21 /* CPU has perfermance counter */ -#define CPU_FEATURE_SCALEFREQ 22 /* CPU supports cpufreq scaling */ -#define CPU_FEATURE_FLATMODE 23 /* CPU has flat mode */ -#define CPU_FEATURE_EIODECODE 24 /* CPU has EXTIOI interrupt pin decode mode */ -#define CPU_FEATURE_GUESTID 25 /* CPU has GuestID feature */ -#define CPU_FEATURE_HYPERVISOR 26 /* CPU has hypervisor (running in VM) */ -#define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */ -#define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */ -#define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ -#define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ -#define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 2 /* CPU has SC.Q instruction */ +#define CPU_FEATURE_UAL 3 /* CPU supports unaligned access */ +#define CPU_FEATURE_FPU 4 /* CPU has FPU */ +#define CPU_FEATURE_LSX 5 /* CPU has LSX (128-bit SIMD) */ +#define CPU_FEATURE_LASX 6 /* CPU has LASX (256-bit SIMD) */ +#define CPU_FEATURE_CRC32 7 /* CPU has CRC32 instructions */ +#define CPU_FEATURE_COMPLEX 8 /* CPU has Complex instructions */ +#define CPU_FEATURE_CRYPTO 9 /* CPU has Crypto instructions */ +#define CPU_FEATURE_LVZ 10 /* CPU has Virtualization extension */ +#define CPU_FEATURE_LBT_X86 11 /* CPU has X86 Binary Translation */ +#define CPU_FEATURE_LBT_ARM 12 /* CPU has ARM Binary Translation */ +#define CPU_FEATURE_LBT_MIPS 13 /* CPU has MIPS Binary Translation */ +#define CPU_FEATURE_TLB 14 /* CPU has TLB */ +#define CPU_FEATURE_CSR 15 /* CPU has CSR */ +#define CPU_FEATURE_IOCSR 16 /* CPU has IOCSR */ +#define CPU_FEATURE_WATCH 17 /* CPU has watchpoint registers */ +#define CPU_FEATURE_VINT 18 /* CPU has vectored interrupts */ +#define CPU_FEATURE_CSRIPI 19 /* CPU has CSR-IPI */ +#define CPU_FEATURE_EXTIOI 20 /* CPU has EXT-IOI */ +#define CPU_FEATURE_PREFETCH 21 /* CPU has prefetch instructions */ +#define CPU_FEATURE_PMP 22 /* CPU has perfermance counter */ +#define CPU_FEATURE_SCALEFREQ 23 /* CPU supports cpufreq scaling */ +#define CPU_FEATURE_FLATMODE 24 /* CPU has flat mode */ +#define CPU_FEATURE_EIODECODE 25 /* CPU has EXTIOI interrupt pin decode mode */ +#define CPU_FEATURE_GUESTID 26 /* CPU has GuestID feature */ +#define CPU_FEATURE_HYPERVISOR 27 /* CPU has hypervisor (running in VM) */ +#define CPU_FEATURE_PTW 28 /* CPU has hardware page table walker */ +#define CPU_FEATURE_LSPW 29 /* CPU has LSPW (lddir/ldpte instructions) */ +#define CPU_FEATURE_MSGINT 30 /* CPU has MSG interrupt */ +#define CPU_FEATURE_AVECINT 31 /* CPU has AVEC interrupt */ +#define CPU_FEATURE_REDIRECTINT 32 /* CPU has interrupt remapping */ #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL) #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU) #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX) diff --git a/arch/loongarch/include/uapi/asm/hwcap.h b/arch/loongarch/include/uapi/asm/hwcap.h index 2b34e56cfa9ed..49519b4362c69 100644 --- a/arch/loongarch/include/uapi/asm/hwcap.h +++ b/arch/loongarch/include/uapi/asm/hwcap.h @@ -18,5 +18,6 @@ #define HWCAP_LOONGARCH_LBT_MIPS (1 << 12) #define HWCAP_LOONGARCH_PTW (1 << 13) #define HWCAP_LOONGARCH_LSPW (1 << 14) +#define HWCAP_LOONGARCH_SCQ (1 << 15) #endif /* _UAPI_ASM_HWCAP_H */ diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c index 08a227034042d..657bbae6c1c7e 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -177,6 +177,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c) c->options |= LOONGARCH_CPU_LAM; elf_hwcap |= HWCAP_LOONGARCH_LAM; } + if (config & CPUCFG2_SCQ) { + c->options |= LOONGARCH_CPU_SCQ; + elf_hwcap |= HWCAP_LOONGARCH_SCQ; + } if (config & CPUCFG2_FP) { c->options |= LOONGARCH_CPU_FPU; elf_hwcap |= HWCAP_LOONGARCH_FPU; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a8800d20e11bd..a60471b964400 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "Features\t\t:"); if (cpu_has_cpucfg) seq_printf(m, " cpucfg"); if (cpu_has_lam) seq_printf(m, " lam"); + if (cpu_has_scq) seq_printf(m, " scq"); if (cpu_has_ual) seq_printf(m, " ual"); if (cpu_has_fpu) seq_printf(m, " fpu"); if (cpu_has_lsx) seq_printf(m, " lsx");