From: H.J. Lu <hongjiu.lu@intel.com>
Date: Sat, 16 Feb 2019 20:29:24 +0000 (+0000)
Subject: i386: Correct *vec_extractv2si_zext_mem
X-Git-Tag: basepoints/gcc-10~1122
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=49be11f5c9376c0b3ee0b4f8a1cc19ca797e9f45;p=thirdparty%2Fgcc.git

i386: Correct *vec_extractv2si_zext_mem

The second and third alternatives in *vec_extractv2si_zext_mem don't
require MMX.  But the second one requires SSE2.

	* config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require
	MMX.  Add isa attribute.

From-SVN: r268963
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index addbd3999322..58e991d94557 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-02-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require
+	MMX.  Add isa attribute.
+
 2019-02-16  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/66152
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index c1e0f2c411e6..b566cc800202 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1354,13 +1354,14 @@
 	  (vec_select:SI
 	    (match_operand:V2SI 1 "memory_operand" "o,o,o")
 	    (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
-  "TARGET_64BIT && TARGET_MMX"
+  "TARGET_64BIT"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
 {
   operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
-})
+}
+  [(set_attr "isa" "*,sse2,*")])
 
 (define_expand "vec_extractv2sisi"
   [(match_operand:SI 0 "register_operand")