From: Linus Torvalds Date: Wed, 17 Jun 2026 09:21:00 +0000 (+0100) Subject: Merge tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4b99990cdf9560e8a071640baf19f312e6ae02f4;p=thirdparty%2Fkernel%2Flinux.git Merge tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel Pull drm updates from Dave Airlie: "Highlights: - xe: add initial CRI platform support - amdgpu: initial HDMI 2.1 FRL support - rust: add some new type concepts for device lifetimes - scheduler: moves to a fair algorithm and lots of cleanups But it's mostly the usual mountain of changes across the board. core: - add docbook for DRM_IOCTL_SYNCOBJ_EVENTFD - change signature of drm_connector_attach_hdr_output_metadata_property - dedup counter and timestamp retrieval in vblank code - parse AMD VSDB v3 in CTA extension blocks - add P230, Y7, XYYY2101010, T430, XVUY210101010 formats - don't call drop master on file close if not master - use drm_printf_indent in atomic / bridge - fix 32b format descriptions - docs: fix toctree - hdmi: add common TMDS character rates - fix drm_syncobj_find_fence leak rust: - introduce Higher-Ranked lifetime types - replace drvdata with scoped registration data - add GPUVM immediate mode abstraction for rust GPU drivers - introduce DeviceContext type state for drm::Device bridge: - clarify drm_bridge_get/put - create drm_get_bridge_by_endpoint and use it - analogix_dp: add panel probing - ite-it6211 - use drm audio hdmi helpers buddy: - add lockdep annotations dp: - add PR and VRR updates - mst: fix buffer overflows - add Adaptive Sync SDP decoding support - fix OOB reads in dp-mst ttm: - bump fpfn/lpfn to 64-bit scheduler: - change default to fair scheduler - map runqueue 1:1 with scheduler dma-buf: - port selftests to kunit - convert dma-buf system/heap allocators to module - add separate DMABUF_HEAPS_SYSTEM_CC_SHARED Kconfig udmabuf: - revert hugetlb support - fix error with CONFIG_DMA_API_DEBUG dma-fence: - fix tracepoints lifetime - remove unused signal on any support ras: - add clear error counter netlink command to drm ras gpusvm: - reject VMAs with VM_IO or VM_PFNMAP when creating SVM ranges - use IOVA allocations pagemap: - use IOVA allocations panels: - update to use ref counts - add support for CSW PNB601LS1-2, LGD LP116WHA-SPB1 - add support for waveshare panels - CMN N116BCN-EA1, CMN N140HCA-EEK, IVO M140NWFQ R5, - IVO, R140NWFW R0, BOE NT140*, BOE NV133FHM-N4F, - AUO B140*, AUO B133HAN06.6 and AUO B116XTN02.3 eDP panels - Surface Pro 12 Panel xe: - add CRI PCI-IDs - debugfs add multi-lrc info - engine init cleanup - PF fair scheduling auto provisioning - system controller support for CRI/Xe3p - PXP state machine fixes - Reset/wedge/unload corner case fixes - Wedge path memory allocation fixes - PAT type cleanups - Reject unsafe PAT for CPU cached memory - OA improvements for CRI device memory - kernel doc syntax in xe headers - xe_drm.h documentation fixes - include guard cleanups - VF CCS memory pool - i915/xe step unification - Xe3p GT tuning fixes - forcewake cleanup in GT and GuC - admin-only PF mode - enable hwmon energy attributes for CRI - enable GT_MI_USER_INTERRUPT - refactor emit functions - oa workarounds - multi_queue: allow QUEUE_TIMESTAMP register - convert stolen memory to ttm range manager - use xe2 style blitter as a feature flag - make drm_driver const - add/use IRQ page to HW engine definition - fix oops when display disabled i915: - enable PIPEDMC_ERROR interrupt - more common display code refactoring - restructure DP/HDMI sink format handling - eliminate FB usage from lowlevel pinning code - panel replay bw optimization - integrate sharpness filter into the scaler - new fb_pin abstraction for xe/i915 fb transparent handling - skip inactive MST connectors on HDCP - start switching to display specific registers - use polling when irq unavailable - Adaptive-sync SDP prep amdgpu: - use drm_display_info for AMD VSDB data - Initial HDMI 2.1 FRL support - Initial DCN 4.2.1 support - GART fixes for non-4k pages - GC 11.5.6/SDMA 6.4.0/and other new IPs - GFX9/DCE6/Hawaii/SDMA4/GART/Userq fixes - Finish support for using multiple SDMA queues for TTM operations - SWSMU updates - GC 12.1 updates - SMU 15.0.8 updates - DCN 4.2 updates - DC type conversion fixes - Enable DC power module - Replay/PSR updates - SMU 13.x updates - Compute queue quantum MQD updates - ASPM fix - Align VKMS with common implementation - DC analog support fixes - UVD 3 fixes - TCC harvesting fixes for SI - GC 11 APU module reload fix - NBIO 6.3.2 support - IH 7.1 updates - DC cursor fixes - VCN/JPEG user fence fixes - DC support for connectors without DDC - Prefer ROM BAR for default VGA device - DC bandwidth fixes - Add PTL support for profiler - Introduce dc_plane_cm and migrate surface update color path - Add FRL registers for HDMI 2.1 - Restructure VM state machine - Auxless ALPM support - GEM_OP locking/warning fixes - switch to system_dfl_wq amdkfd: - GPUVM TLB flush fix - Hotplug fix - Boundary check fixes - SVM fixes - CRIU fixes - add profiler API - MES 12.1 updates msm: - core: - fix shrinker documentation - IFPC enabled for gen8 - PERFCNTR_CONFIG ioctl support - GPU: - reworked UBWC handling - a810 support - MDSS: - add support for Milos platform - reworked UBWC handling - DisplayPort: - reworked HPD handling as prep for MST - DPU: - Milos platform support - reworked UBWC handling - DSI: - Milos platform support nova: - Hopper/Blackwell enablement (GH100/GB100/GB202) - FSP support - 32-bit firmware support - HAL functions - refactor GSP boot/unload - GA100 support - VBIOS hardening/refactoring - Adopt higher order lifetime types tyr: - define register blocks - add shmem backed GEM objects - adopt higher order lifetime types - move clock cleanup into Drop radeon: - Hawaii SMU fixes - CS parser fix - use struct drm_edid instead of edid amdxdna: - export per-client BO memory via fdinfo - AIE4 device support - support medium/lower power modes - expandable device heap support - revert read-only user-pointer BO mappings ivpu: - support frequency limiting panthor: - enable GEM shrinker support - add eviction and reclaim info to fdinfo v3d: - enable runtime PM mgag200: - support XRGB1555 + C8 ast: - support XRGB1555 + C8 - use constants for lots of registers - fix register handling imagination: - fence handling refactoring nouveau: - fix sched double call - expose VBIOS on GSP-RM systems - add GA100 support virtio: - add VIRTIO_GPU_F_BLOB_ALIGNMENT flag - add deferred mapping support gud: - add RCade Display Adapter hibmc: - fix no connectors usage mediatek: - hdmi: convert error handling - simplify mtk_crtc allocation exynos: - move fbdev emulation to drm client buffers - use drm format helpers for geometry/size - adopt core DMA tracking - fix framebuffer offset handling renesas: - add RZ/T2H SOC support versilicon: - add cursor plane support tegra: - use drm client for framebuffer" * tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel: (1731 commits) dma-buf: move system_cc_shared heap under separate Kconfig accel/amdxdna: Clear sva pointer after unbind agp/amd64: Fix broken error propagation in agp_amd64_probe() accel/amdxdna: Require carveout when PASID and force_iova are disabled drm/amdkfd: always resume_all after suspend_all drm/amdgpu/gfx: move fault and EOP IRQ get/put to hw_init/hw_fini drm/amd/display: Consult MCCS FreeSync cap only if requested & supported drm/amd/pm: Use strscpy in profile mode parsing drm/amdkfd: Fix infinite loop parsing CRAT with zero subtype length drm/amdkfd: fix sysfs topology prop length on buffer truncation drm/amdgpu: drop retry loop in amdgpu_hmm_range_get_pages drm/amd/pm: bound OD parameter parsing to stack array size drm/amd/pm: Stop pp_od_clk_voltage emit at PAGE_SIZE drm/amdkfd: Unwind debug trap enable on copy_to_user failure drm/amdgpu: validate the mes firmware version for gfx12.1 drm/amdgpu: validate the mes firmware version for gfx12 drm/amdgpu: compare MES firmware version ucode for gfx11 drm/amdkfd: Add bounds check for AMDKFD_IOC_WAIT_EVENTS drm/amdgpu: restart the CS if some parts of the VM are still invalidated drm/amd/display: use unsigned types for local pipe and REG_GET counters ... --- 4b99990cdf9560e8a071640baf19f312e6ae02f4 diff --cc drivers/gpu/drm/drm_atomic.c index 0eb52d1d5af23,170de30c28ae4..080aec5a97746 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@@ -824,26 -824,26 +824,26 @@@ static void drm_atomic_colorop_print_st switch (colorop->type) { case DRM_COLOROP_1D_CURVE: - drm_printf(p, "\tcurve_1d_type=%s\n", - drm_get_colorop_curve_1d_type_name(state->curve_1d_type)); + drm_printf_indent(p, 1, "curve_1d_type=%s\n", + drm_get_colorop_curve_1d_type_name(state->curve_1d_type)); break; case DRM_COLOROP_1D_LUT: - drm_printf(p, "\tsize=%d\n", colorop->size); - drm_printf(p, "\tinterpolation=%s\n", - drm_get_colorop_lut1d_interpolation_name(state->lut1d_interpolation)); - drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0); + drm_printf_indent(p, 1, "size=%d\n", colorop->size); + drm_printf_indent(p, 1, "interpolation=%s\n", - drm_get_colorop_lut1d_interpolation_name(colorop->lut1d_interpolation)); ++ drm_get_colorop_lut1d_interpolation_name(state->lut1d_interpolation)); + drm_printf_indent(p, 1, "data blob id=%d\n", state->data ? state->data->base.id : 0); break; case DRM_COLOROP_CTM_3X4: - drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0); + drm_printf_indent(p, 1, "data blob id=%d\n", state->data ? state->data->base.id : 0); break; case DRM_COLOROP_MULTIPLIER: - drm_printf(p, "\tmultiplier=%llu\n", state->multiplier); + drm_printf_indent(p, 1, "multiplier=%llu\n", state->multiplier); break; case DRM_COLOROP_3D_LUT: - drm_printf(p, "\tsize=%d\n", colorop->size); - drm_printf(p, "\tinterpolation=%s\n", - drm_get_colorop_lut3d_interpolation_name(state->lut3d_interpolation)); - drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0); + drm_printf_indent(p, 1, "size=%d\n", colorop->size); + drm_printf_indent(p, 1, "interpolation=%s\n", - drm_get_colorop_lut3d_interpolation_name(colorop->lut3d_interpolation)); ++ drm_get_colorop_lut3d_interpolation_name(state->lut3d_interpolation)); + drm_printf_indent(p, 1, "data blob id=%d\n", state->data ? state->data->base.id : 0); break; default: break; diff --cc drivers/gpu/drm/drm_colorop.c index 509678e5371fa,764d120606665..65fec53f70fa6 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@@ -514,25 -516,11 +514,25 @@@ static void __drm_colorop_state_reset(s colorop_state->bypass = true; if (colorop->curve_1d_type_property) { - drm_object_property_get_default_value(&colorop->base, - colorop->curve_1d_type_property, - &val); - colorop_state->curve_1d_type = val; + if (!drm_object_property_get_default_value(&colorop->base, + colorop->curve_1d_type_property, + &val)) + colorop_state->curve_1d_type = val; } + + if (colorop->lut1d_interpolation_property) { + if (!drm_object_property_get_default_value(&colorop->base, + colorop->lut1d_interpolation_property, + &val)) + colorop_state->lut1d_interpolation = val; + } + + if (colorop->lut3d_interpolation_property) { + if (!drm_object_property_get_default_value(&colorop->base, + colorop->lut3d_interpolation_property, + &val)) + colorop_state->lut3d_interpolation = val; + } } /** diff --cc drivers/gpu/drm/panthor/panthor_mmu.c index b12c641af46c8,9d45008505619..dab6840e88575 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@@ -1180,6 -1235,44 +1235,44 @@@ panthor_vm_op_ctx_prealloc_vmas(struct return 0; } + static void panthor_vm_init_op_ctx(struct panthor_vm_op_ctx *op_ctx, + u64 size, u64 va, u32 flags) + { + memset(op_ctx, 0, sizeof(*op_ctx)); + op_ctx->flags = flags; + op_ctx->va.range = size; + op_ctx->va.addr = va; + } + + static int panthor_vm_op_ctx_prealloc_pts(struct panthor_vm_op_ctx *op_ctx) + { + u64 size = op_ctx->va.range; + u64 va = op_ctx->va.addr; - int ret; + + /* L1, L2 and L3 page tables. + * We could optimize L3 allocation by iterating over the sgt and merging + * 2M contiguous blocks, but it's simpler to over-provision and return + * the pages if they're not used. + */ + u64 pt_count = ((ALIGN(va + size, 1ull << 39) - ALIGN_DOWN(va, 1ull << 39)) >> 39) + + ((ALIGN(va + size, 1ull << 30) - ALIGN_DOWN(va, 1ull << 30)) >> 30) + + ((ALIGN(va + size, 1ull << 21) - ALIGN_DOWN(va, 1ull << 21)) >> 21); + + op_ctx->rsvd_page_tables.pages = kzalloc_objs(*op_ctx->rsvd_page_tables.pages, + pt_count); + if (!op_ctx->rsvd_page_tables.pages) + return -ENOMEM; + - ret = kmem_cache_alloc_bulk(pt_cache, GFP_KERNEL, pt_count, - op_ctx->rsvd_page_tables.pages); - op_ctx->rsvd_page_tables.count = ret; - if (ret != pt_count) ++ if (!kmem_cache_alloc_bulk(pt_cache, GFP_KERNEL, pt_count, ++ op_ctx->rsvd_page_tables.pages)) { ++ op_ctx->rsvd_page_tables.count = 0; + return -ENOMEM; ++ } ++ op_ctx->rsvd_page_tables.count = pt_count; + + return 0; + } + #define PANTHOR_VM_BIND_OP_MAP_FLAGS \ (DRM_PANTHOR_VM_BIND_OP_MAP_READONLY | \ DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC | \ diff --cc drivers/gpu/nova-core/vbios.rs index 8b7d17a246602,fd168c5da78cd..c6e6bfcd6a1f8 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@@ -912,109 -887,48 +889,48 @@@ impl PmuLookupTable } } - impl FwSecBiosBuilder { - fn setup_falcon_data( - &mut self, - pci_at_image: &PciAtBiosImage, - first_fwsec: &FwSecBiosBuilder, - ) -> Result { - let mut offset = usize::from_safe_cast(pci_at_image.falcon_data_ptr()?); - let mut pmu_in_first_fwsec = false; - - // The falcon data pointer assumes that the PciAt and FWSEC images - // are contiguous in memory. However, testing shows the EFI image sits in - // between them. So calculate the offset from the end of the PciAt image - // rather than the start of it. Compensate. - offset -= pci_at_image.base.data.len(); - - // The offset is now from the start of the first Fwsec image, however - // the offset points to a location in the second Fwsec image. Since - // the fwsec images are contiguous, subtract the length of the first Fwsec - // image from the offset to get the offset to the start of the second - // Fwsec image. - if offset < first_fwsec.base.data.len() { - pmu_in_first_fwsec = true; - } else { - offset -= first_fwsec.base.data.len(); - } - - self.falcon_data_offset = Some(offset); - - if pmu_in_first_fwsec { - self.pmu_lookup_table = Some(PmuLookupTable::new( - &self.base.dev, - &first_fwsec.base.data[offset..], - )?); - } else { - self.pmu_lookup_table = Some(PmuLookupTable::new( - &self.base.dev, - &self.base.data[offset..], - )?); - } - - match self - .pmu_lookup_table - .as_ref() - .ok_or(EINVAL)? - .find_entry_by_type(FALCON_UCODE_ENTRY_APPID_FWSEC_PROD) - { - Ok(entry) => { - let mut ucode_offset = usize::from_safe_cast(entry.data); - ucode_offset -= pci_at_image.base.data.len(); - if ucode_offset < first_fwsec.base.data.len() { - dev_err!(self.base.dev, "Falcon Ucode offset not in second Fwsec.\n"); - return Err(EINVAL); - } - ucode_offset -= first_fwsec.base.data.len(); - self.falcon_ucode_offset = Some(ucode_offset); - } - Err(e) => { - dev_err!( - self.base.dev, - "PmuLookupTableEntry not found, error: {:?}\n", - e - ); - return Err(EINVAL); - } - } - Ok(()) - } - - /// Build the final FwSecBiosImage from this builder - fn build(self) -> Result { - let ret = FwSecBiosImage { - base: self.base, - falcon_ucode_offset: self.falcon_ucode_offset.ok_or(EINVAL)?, - }; + impl FwSecBiosImage { + /// Build the final `FwSecBiosImage` from the PCI-AT and FWSEC BIOS images. + fn new( + dev: &device::Device, + pci_at_image: PciAtBiosImage, + data: KVVec, + ) -> Result { + let offset = pci_at_image.falcon_data_offset(dev)?; + + let pmu_lookup_data = data.get(offset..).ok_or(EINVAL)?; + let pmu_lookup_table = PmuLookupTable::new(dev, pmu_lookup_data)?; + + let entry = pmu_lookup_table + .find_entry_by_type(PmuLookupTableEntry::APPID_FWSEC_PROD) + .inspect_err(|e| { + dev_err!(dev, "PmuLookupTableEntry not found, error: {:?}\n", e); + })?; - if cfg!(debug_assertions) { - // Print the desc header for debugging - let desc = ret.header()?; - dev_dbg!(ret.base.dev, "PmuLookupTableEntry desc: {:#?}\n", desc); - } + let falcon_ucode_offset = usize::from_safe_cast(entry.data) + .checked_sub(pci_at_image.base.data.len()) + .ok_or(EINVAL) + .inspect_err(|_| { + dev_err!(dev, "Falcon Ucode offset not in Fwsec.\n"); + })?; - Ok(ret) + Ok(FwSecBiosImage { + dev: dev.into(), + data, + falcon_ucode_offset, + }) } - } - impl FwSecBiosImage { /// Get the FwSec header ([`FalconUCodeDesc`]). pub(crate) fn header(&self) -> Result { - // Get the falcon ucode offset that was found in setup_falcon_data. - let falcon_ucode_offset = self.falcon_ucode_offset; + let data = self.data.get(self.falcon_ucode_offset..).ok_or(EINVAL)?; - // Read the first 4 bytes to get the version. - let hdr_bytes: [u8; 4] = self.base.data[falcon_ucode_offset..falcon_ucode_offset + 4] - .try_into() - .map_err(|_| EINVAL)?; - let hdr = u32::from_le_bytes(hdr_bytes); - let ver = (hdr & 0xff00) >> 8; - - let data = self.base.data.get(falcon_ucode_offset..).ok_or(EINVAL)?; + // Read the version byte from the header. + let ver = data.get(1).copied().ok_or(EINVAL)?; match ver { 2 => { - let v2 = FalconUCodeDescV2::from_bytes_copy_prefix(data) - .ok_or(EINVAL)? + let v2 = FalconUCodeDescV2::read_from_prefix(data) + .map_err(|_| EINVAL)? .0; Ok(FalconUCodeDesc::V2(v2)) } diff --cc include/drm/drm_colorop.h index d5b45339333f2,c873199c60da9..d08a6a8a83922 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@@ -183,22 -183,8 +183,22 @@@ struct drm_colorop_state */ struct drm_property_blob *data; + /** + * @lut1d_interpolation: + * + * Interpolation for DRM_COLOROP_1D_LUT + */ + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation; + + /** + * @lut3d_interpolation: + * + * Interpolation for DRM_COLOROP_3D_LUT + */ + enum drm_colorop_lut3d_interpolation_type lut3d_interpolation; + - /** @state: backpointer to global drm_atomic_state */ - struct drm_atomic_state *state; + /** @state: backpointer to global drm_atomic_commit */ + struct drm_atomic_commit *state; }; /**