From: Haochen Jiang <haochen.jiang@intel.com>
Date: Thu, 30 Dec 2021 07:47:58 +0000 (+0800)
Subject: Extend predicate of operands[1] from register_operand to vector_operand for andnot... 
X-Git-Tag: basepoints/gcc-13~1885
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4bb79e27c02c5cd57d5781bef20e70982d898c40;p=thirdparty%2Fgcc.git

Extend predicate of operands[1] from register_operand to vector_operand for andnot insn.

This can do optimization like

-       pcmpeqd %xmm0, %xmm0
-       pxor    g(%rip), %xmm0
-       pand    %xmm1, %xmm0
+       movdqa  g(%rip), %xmm0
+       pandn   %xmm1, %xmm0

gcc/ChangeLog:

	PR target/53652
	* config/i386/sse.md (*andnot<mode>3): Extend predicate of
	operands[1] from register_operand to vector_operand.

gcc/testsuite/ChangeLog:

	PR target/53652
	* gcc.target/i386/pr53652-1.c: New test.
---

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d8f303511c1a..0864748875e3 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16631,7 +16631,7 @@
 (define_insn "*andnot<mode>3"
   [(set (match_operand:VI 0 "register_operand" "=x,x,v")
 	(and:VI
-	  (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
+	  (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
 	  (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
   "TARGET_SSE"
 {
diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c b/gcc/testsuite/gcc.target/i386/pr53652-1.c
new file mode 100644
index 000000000000..bd07ee29f4de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
+/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
+
+typedef unsigned long long vec __attribute__((vector_size (16)));
+vec g;
+vec f1 (vec a, vec b)
+{
+  return ~a&b;
+}
+vec f2 (vec a, vec b)
+{
+  return ~g&b;
+}
+