From: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Tue, 24 May 2022 13:03:47 +0000 (+0200)
Subject: RISC-V: add consecutive_bits_operand predicate
X-Git-Tag: basepoints/gcc-14~6120
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4bf0dcb0492c40be7e0603b13a8b5949609388dd;p=thirdparty%2Fgcc.git

RISC-V: add consecutive_bits_operand predicate

Provide an easy way to constrain for constants that are a a single,
consecutive run of ones.

gcc/ChangeLog:

	* config/riscv/predicates.md (consecutive_bits_operand):
	Implement new predicate.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index c37caa2502b..90db5dfcdd5 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -243,3 +243,14 @@
 (define_predicate "imm5_operand"
   (and (match_code "const_int")
        (match_test "INTVAL (op) < 5")))
+
+;; A CONST_INT operand that consists of a single run of consecutive set bits.
+(define_predicate "consecutive_bits_operand"
+  (match_code "const_int")
+{
+	unsigned HOST_WIDE_INT val = UINTVAL (op);
+	if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0)
+	        return false;
+
+	return true;
+})