From: Richard Henderson Date: Wed, 8 Oct 2025 21:55:29 +0000 (-0700) Subject: target/arm: Support page protections for GCS mmu indexes X-Git-Tag: v10.2.0-rc1~67^2~47 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4c14265b8092a250edaef62891ee2d55fcfac92d;p=thirdparty%2Fqemu.git target/arm: Support page protections for GCS mmu indexes Take read and write from the s1perms.gcs bit computed by the Arm pseudocode. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6c52ed1ad0..d4386ede73 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1619,12 +1619,16 @@ static int get_S1prot_indirect(CPUARMState *env, S1Translate *ptw, } } - if (perm & PAGE_WXN) { + if (regime_is_gcs(mmu_idx)) { + /* + * Note that the one s1perms.gcs bit controls both read and write + * access via AccessType_GCS. See AArch64.S1CheckPermissions. + */ + perm = (perm & PAGE_GCS ? PAGE_READ | PAGE_WRITE : 0); + } else if (perm & PAGE_WXN) { perm &= ~PAGE_EXEC; } - /* TODO: FEAT_GCS */ - return perm & PAGE_RWX; } @@ -2277,6 +2281,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ prot = get_S1prot_indirect(env, ptw, mmu_idx, pi, po, result->f.attrs.space, out_space); + } else if (regime_is_gcs(mmu_idx)) { + /* + * While one must use indirect permissions to successfully + * use GCS instructions, AArch64.S1DirectBasePermissions + * faithfully supplies s1perms.gcs = 0, Just In Case. + */ + prot = 0; } else { int xn = extract64(attrs, 54, 1); int pxn = extract64(attrs, 53, 1);