From: Julian Seward <jseward@acm.org>
Date: Sun, 1 May 2011 18:36:51 +0000 (+0000)
Subject: When simplifying (improving) the IR generated by the ARM front end, do
X-Git-Tag: svn/VALGRIND_3_7_0^2~87
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4d080dc1447020e1fdc489943931dfd204c5d299;p=thirdparty%2Fvalgrind.git

When simplifying (improving) the IR generated by the ARM front end, do
CSE by default.  This significantly improves performance for ARM (not
Thumb) code that leans heavily on predicated instructions by commoning
up duplicate condition code evaluations within a single IRSB.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2137
---

diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c
index 504105b1f4..5cf91dc456 100644
--- a/VEX/priv/ir_opt.c
+++ b/VEX/priv/ir_opt.c
@@ -4714,6 +4714,7 @@ IRSB* do_iropt_BB(
       bb = cprop_BB(bb);
       bb = spec_helpers_BB ( bb, specHelper );
       redundant_put_removal_BB ( bb, preciseMemExnsFn );
+      do_cse_BB( bb );
       do_deadcode_BB( bb );
    }