From: Jeff Law Date: Mon, 13 Jul 1998 12:08:59 +0000 (-0600) Subject: mn10300.h (REG_CLASS_FROM_LETTER): Map 'y' to SP_REGS. X-Git-Tag: prereleases/egcs-1.1-prerelease~282 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4d1a91c2bf4e81b4c260a072c411d3bfc5ca6dd8;p=thirdparty%2Fgcc.git mn10300.h (REG_CLASS_FROM_LETTER): Map 'y' to SP_REGS. * mn10300.h (REG_CLASS_FROM_LETTER): Map 'y' to SP_REGS. Handle 'x' as NO_REGS for this cpu. (REGNO_OK_FOR_BIT_BASE_P): Define. (REG_OK_FOR_BIT_BASE_P): Define. (GO_IF_LEGITIMATE_ADDRESS): Use them. (REG_OK_FOR_INDEX_P): Tweak. * mn13000.c (REG_SAVE_BYTES): Define. (expand_epilogue, initial_offset): Use it. (secondary_reload_class): Slightly reformat. (output_tst): Tweak comments. * mn10300.md: Change 'x' to 'y' for SP_REGS. Then add 'x' to many patterns. (addsi3): Turn into a define_expand/define_insn pair. Rework code for three operand addition case to be more efficient. (subsi3): Turn into a define_expand/define_insn pair. From-SVN: r21104 --- diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index d813f2c32ccd..7456c32febed 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -36,6 +36,11 @@ Boston, MA 02111-1307, USA. */ #include "tree.h" #include "obstack.h" +/* The size of the callee register save area. Right now we save everything + on entry since it costs us nothing in code size. It does cost us from a + speed standpoint, so we want to optimize this sooner or later. */ +#define REG_SAVE_BYTES (16) + /* Global registers known to hold the value zero. Normally we'd depend on CSE and combine to put zero into a @@ -439,8 +444,8 @@ expand_prologue () /* Determine if it is profitable to put the value zero into a register for the entire function. If so, set ZERO_DREG and ZERO_AREG. */ if (regs_ever_live[2] || regs_ever_live[3] - || regs_ever_live[6] || regs_ever_live[7] - || frame_pointer_needed) + || regs_ever_live[6] || regs_ever_live[7] + || frame_pointer_needed) { int dreg_count, areg_count; @@ -569,7 +574,7 @@ expand_epilogue () } else if ((regs_ever_live[2] || regs_ever_live[3] || regs_ever_live[6] || regs_ever_live[7]) - && size + 16 > 255) + && size + REG_SAVE_BYTES > 255) { emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, @@ -585,7 +590,7 @@ expand_epilogue () if (regs_ever_live[2] || regs_ever_live[3] || regs_ever_live[6] || regs_ever_live[7] || frame_pointer_needed) - emit_jump_insn (gen_return_internal_regs (GEN_INT (size + 16))); + emit_jump_insn (gen_return_internal_regs (GEN_INT (size + REG_SAVE_BYTES))); else { if (size) @@ -689,7 +694,9 @@ secondary_reload_class (class, mode, in) if (GET_CODE (in) == MEM && (mode == QImode || mode == HImode) && (class == ADDRESS_REGS || class == SP_REGS)) - return DATA_REGS; + { + return DATA_REGS; + } /* We can't directly load sp + const_int into a data register; we must use an address register as an intermediate. */ @@ -705,9 +712,10 @@ secondary_reload_class (class, mode, in) if (GET_CODE (in) == PLUS && (XEXP (in, 0) == stack_pointer_rtx || XEXP (in, 1) == stack_pointer_rtx)) - return DATA_REGS; + { + return DATA_REGS; + } - /* Otherwise assume no secondary reloads are needed. */ return NO_REGS; } @@ -723,7 +731,7 @@ initial_offset (from, to) if (regs_ever_live[2] || regs_ever_live[3] || regs_ever_live[6] || regs_ever_live[7] || frame_pointer_needed) - return 16; + return REG_SAVE_BYTES; else return 0; } @@ -736,7 +744,7 @@ initial_offset (from, to) if (regs_ever_live[2] || regs_ever_live[3] || regs_ever_live[6] || regs_ever_live[7] || frame_pointer_needed) - return (get_frame_size () + 16 + return (get_frame_size () + REG_SAVE_BYTES + (current_function_outgoing_args_size ? current_function_outgoing_args_size + 4 : 0)); else @@ -950,7 +958,10 @@ output_tst (operand, insn) If it's a call clobbered register, have we past a call? Make sure the register we find isn't the same as ourself; - the mn10300 can't encode that. */ + the mn10300 can't encode that. + + ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN + so the code to detect calls here isn't doing anything useful. */ if (REG_P (SET_DEST (set)) && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) && !reg_set_between_p (SET_DEST (set), temp, insn) diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index ac1fe2e025af..eea94a2d2444 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Matsushita MN10300 series - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GNU CC. @@ -209,7 +209,9 @@ extern struct rtx_def *zero_areg; class that represents their union. */ enum reg_class { - NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES + NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, + DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, + GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES @@ -244,10 +246,9 @@ enum reg_class { #define REGNO_REG_CLASS(REGNO) \ ((REGNO) < 4 ? DATA_REGS : \ (REGNO) < 9 ? ADDRESS_REGS : \ - (REGNO) == 9 ? SP_REGS: 0) + (REGNO) == 9 ? SP_REGS : 0) /* The class value for index registers, and the one for base regs. */ - #define INDEX_REG_CLASS DATA_REGS #define BASE_REG_CLASS SP_OR_ADDRESS_REGS @@ -256,7 +257,7 @@ enum reg_class { #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'd' ? DATA_REGS : \ (C) == 'a' ? ADDRESS_REGS : \ - (C) == 'x' ? SP_REGS : NO_REGS) + (C) == 'y' ? SP_REGS : NO_REGS) /* Macros to check register numbers against specific register classes. */ @@ -270,6 +271,10 @@ enum reg_class { (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER) \ || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER)) +#define REGNO_OK_FOR_BIT_BASE_P(regno) \ + (((regno) > 3 && regno < 10) \ + || (reg_renumber[regno] > 3 && reg_renumber[regno] < 10)) + #define REGNO_OK_FOR_INDEX_P(regno) \ (((regno) >= 0 && regno < 4) \ || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4)) @@ -585,11 +590,11 @@ extern struct rtx_def *mn10300_builtin_saveregs (); && GET_MODE (OP) == QImode \ && (CONSTANT_ADDRESS_P (XEXP (OP, 0)) \ || (GET_CODE (XEXP (OP, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \ + && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0)) \ && XEXP (OP, 0) != stack_pointer_rtx) \ || (GET_CODE (XEXP (OP, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0)) \ + && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0)) \ && XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx \ && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT \ && INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1)))))) @@ -618,16 +623,20 @@ extern struct rtx_def *mn10300_builtin_saveregs (); /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ - ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER) + ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= 10) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) \ - ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= FIRST_PSEUDO_REGISTER) + ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= 10) +#define REG_OK_FOR_BIT_BASE_P(X) \ + ((REGNO (X) >= 4 && REGNO(X) <= 9)) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BIT_BASE_P(X) REGNO_OK_FOR_BIT_BASE_P (REGNO (X)) #endif diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index 502de96c66da..d8f506a36a54 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -57,8 +57,8 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d,*a,d,*a,d,*a,d,*a,d,m") - (match_operand:QI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))] + [(set (match_operand:QI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m") + (match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)" "* @@ -112,8 +112,8 @@ }") (define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d,*a,d,*a,d,*a,d,*a,d,m") - (match_operand:HI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))] + [(set (match_operand:HI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m") + (match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))] "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)" "* @@ -206,9 +206,9 @@ (define_insn "" [(set (match_operand:SI 0 "general_operand" - "=d,a,d,a,dm,dm,am,am,d,d,a,a,aR,x") + "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,y") (match_operand:SI 1 "general_operand" - "0,0,I,I,d,a,d,a,dim,aim,dim,aim,x,aR"))] + "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,xy,axR"))] "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" "* @@ -263,8 +263,8 @@ }") (define_insn "" - [(set (match_operand:SF 0 "general_operand" "=d,a,d,a,dam,da") - (match_operand:SF 1 "general_operand" "0,0,G,G,da,daim"))] + [(set (match_operand:SF 0 "general_operand" "=dx,ax,dx,ax,daxm,dax") + (match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxim"))] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "* @@ -312,9 +312,9 @@ (define_insn "" [(set (match_operand:DI 0 "general_operand" - "=d,a,d,a,dm,dm,am,am,d,d,a,a") + "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax") (match_operand:DI 1 "general_operand" - "0,0,I,I,d,a,d,a,dim,aim,dim,aim"))] + "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))] "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)" "* @@ -473,9 +473,9 @@ (define_insn "" [(set (match_operand:DF 0 "general_operand" - "=d,a,d,a,dm,dm,am,am,d,d,a,a") + "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax") (match_operand:DF 1 "general_operand" - "0,0,G,G,d,a,d,a,dim,aim,dim,aim"))] + "0,0,G,G,dx,ax,dx,ax,dxim,axim,dxim,axim"))] "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)" "* @@ -629,19 +629,19 @@ ;; Go ahead and define tstsi so we can eliminate redundant tst insns ;; when we start trying to optimize this port. (define_insn "tstsi" - [(set (cc0) (match_operand:SI 0 "register_operand" "da"))] + [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))] "" "* return output_tst (operands[0], insn);" [(set_attr "cc" "set_znv")]) (define_insn "" - [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "d")))] + [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))] "" "* return output_tst (operands[0], insn);" [(set_attr "cc" "set_znv")]) (define_insn "" - [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "d")))] + [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))] "" "* return output_tst (operands[0], insn);" [(set_attr "cc" "set_znv")]) @@ -649,8 +649,8 @@ (define_insn "cmpsi" [(set (cc0) - (compare (match_operand:SI 0 "register_operand" "!*d*a,da") - (match_operand:SI 1 "nonmemory_operand" "!*0,dai")))] + (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax") + (match_operand:SI 1 "nonmemory_operand" "!*0,daxi")))] "" "@ add 0,%0 @@ -682,27 +682,60 @@ }") (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d,a,a,da,x,&!da") - (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,da") - (match_operand:SI 2 "nonmemory_operand" "J,J,L,dai,i,da")))] + [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax") + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax") + (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))] "" - "@ - inc %0 - inc %0 - inc4 %0 - add %2,%0 - add %2,%0 - mov %2,%0\;add %1,%0" + "* +{ + switch (which_alternative) + { + case 0: + case 1: + return \"inc %0\"; + case 2: + return \"inc4 %0\"; + case 3: + case 4: + return \"add %2,%0\"; + case 5: + /* I'm not sure if this can happen or not. Might as well be prepared + and generate the best possible code if it does happen. */ + if (true_regnum (operands[0]) == true_regnum (operands[1])) + return \"add %2,%0\"; + if (true_regnum (operands[0]) == true_regnum (operands[2])) + return \"add %1,%0\"; + + /* We have to copy one of the sources into the destination, then add + the other source to the destination. + + Carefully select which source to copy to the destination; a naive + implementation will waste a byte when the source classes are different + and the destination is an address register. Selecting the lowest + cost register copy will optimize this sequence. */ + if (REGNO_REG_CLASS (true_regnum (operands[1])) + == REGNO_REG_CLASS (true_regnum (operands[0]))) + return \"mov %1,%0\;add %2,%0\"; + return \"mov %2,%0\;add %1,%0\"; + } +}" [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")]) ;; ---------------------------------------------------------------------- ;; SUBTRACT INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "subsi3" - [(set (match_operand:SI 0 "register_operand" "=da") +(define_expand "subsi3" + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + "") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=dax") (minus:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "dai")))] + (match_operand:SI 2 "nonmemory_operand" "daxi")))] "" "sub %2,%0" [(set_attr "cc" "set_zn")]) @@ -726,9 +759,9 @@ ;; ---------------------------------------------------------------------- (define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (mult:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "register_operand" "d")))] + (match_operand:SI 2 "register_operand" "dx")))] "" "* { @@ -740,9 +773,9 @@ [(set_attr "cc" "set_zn")]) (define_insn "udivmodsi4" - [(set (match_operand:SI 0 "general_operand" "=d") + [(set (match_operand:SI 0 "general_operand" "=dx") (udiv:SI (match_operand:SI 1 "general_operand" "0") - (match_operand:SI 2 "general_operand" "d"))) + (match_operand:SI 2 "general_operand" "dx"))) (set (match_operand:SI 3 "general_operand" "=&d") (umod:SI (match_dup 1) (match_dup 2)))] "" @@ -761,9 +794,9 @@ [(set_attr "cc" "set_zn")]) (define_insn "divmodsi4" - [(set (match_operand:SI 0 "general_operand" "=d") + [(set (match_operand:SI 0 "general_operand" "=dx") (div:SI (match_operand:SI 1 "general_operand" "0") - (match_operand:SI 2 "general_operand" "d"))) + (match_operand:SI 2 "general_operand" "dx"))) (set (match_operand:SI 3 "general_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] "" @@ -782,9 +815,9 @@ ;; ---------------------------------------------------------------------- (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d") + [(set (match_operand:SI 0 "register_operand" "=dx,dx") (and:SI (match_operand:SI 1 "register_operand" "%0,0") - (match_operand:SI 2 "nonmemory_operand" "N,di")))] + (match_operand:SI 2 "nonmemory_operand" "N,dxi")))] "" "* { @@ -817,9 +850,9 @@ ;; ---------------------------------------------------------------------- (define_insn "iorsi3" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (ior:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "nonmemory_operand" "di")))] + (match_operand:SI 2 "nonmemory_operand" "dxi")))] "" "or %2,%0" [(set_attr "cc" "set_znv")]) @@ -829,9 +862,9 @@ ;; ---------------------------------------------------------------------- (define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (xor:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "nonmemory_operand" "di")))] + (match_operand:SI 2 "nonmemory_operand" "dxi")))] "" "xor %2,%0" [(set_attr "cc" "set_znv")]) @@ -841,7 +874,7 @@ ;; ---------------------------------------------------------------------- (define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (not:SI (match_operand:SI 1 "register_operand" "0")))] "" "not %0" @@ -897,7 +930,7 @@ (define_insn "" [(set (cc0) - (zero_extract:SI (match_operand:SI 0 "register_operand" "d") + (zero_extract:SI (match_operand:SI 0 "register_operand" "dx") (match_operand 1 "const_int_operand" "") (match_operand 2 "const_int_operand" "")))] "" @@ -924,7 +957,7 @@ (define_insn "" [(set (cc0) - (zero_extract:SI (match_operand:QI 0 "general_operand" "R,d") + (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx") (match_operand 1 "const_int_operand" "") (match_operand 2 "const_int_operand" "")))] "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))" @@ -968,7 +1001,7 @@ [(set_attr "cc" "set_znv")]) (define_insn "" - [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "d") + [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx") (match_operand:SI 1 "const_int_operand" "")))] "" "btst %1,%0" @@ -977,7 +1010,7 @@ (define_insn "" [(set (cc0) (and:SI - (subreg:SI (match_operand:QI 0 "general_operand" "R,d") 0) + (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0) (match_operand:SI 1 "const_8bit_operand" "")))] "" "@ @@ -1188,7 +1221,7 @@ }") (define_insn "call_value_internal" - [(set (match_operand 0 "" "=da") + [(set (match_operand 0 "" "=dax") (call (mem:QI (match_operand:SI 1 "call_address_operand" "aS")) (match_operand:SI 2 "general_operand" "g")))] "" @@ -1232,7 +1265,7 @@ ;; ---------------------------------------------------------------------- (define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") + [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx") (zero_extend:SI (match_operand:QI 1 "general_operand" "0,d,m")))] "" @@ -1243,9 +1276,9 @@ [(set_attr "cc" "none_0hit")]) (define_insn "zero_extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") + [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx") (zero_extend:SI - (match_operand:HI 1 "general_operand" "0,d,m")))] + (match_operand:HI 1 "general_operand" "0,dx,m")))] "" "@ exthu %0 @@ -1256,9 +1289,9 @@ ;;- sign extension instructions (define_insn "extendqisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d") + [(set (match_operand:SI 0 "general_operand" "=dx,dx") (sign_extend:SI - (match_operand:QI 1 "general_operand" "0,d")))] + (match_operand:QI 1 "general_operand" "0,dx")))] "" "@ extb %0 @@ -1266,9 +1299,9 @@ [(set_attr "cc" "none_0hit")]) (define_insn "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d") + [(set (match_operand:SI 0 "general_operand" "=dx,dx") (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,d")))] + (match_operand:HI 1 "general_operand" "0,dx")))] "" "@ exth %0 @@ -1280,10 +1313,10 @@ ;; ---------------------------------------------------------------------- (define_insn "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "=da,d,d,d,d") + [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx") (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,0,0") - (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,di")))] + (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))] "" "@ add %0,%0 @@ -1294,19 +1327,19 @@ [(set_attr "cc" "set_zn")]) (define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "di")))] + (match_operand:QI 2 "nonmemory_operand" "dxi")))] "" "lsr %S2,%0" [(set_attr "cc" "set_zn")]) (define_insn "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "di")))] + (match_operand:QI 2 "nonmemory_operand" "dxi")))] "" "asr %S2,%0" [(set_attr "cc" "set_zn")]) @@ -1341,13 +1374,19 @@ (match_operand:SI 0 "const_int_operand" "i") (return)] "" - "ret [d2,d3,a2,a3],%0" + "* +{ + return \"ret [d2,d3,a2,a3],%0\"; +}" [(set_attr "cc" "clobber")]) (define_insn "store_movm" [(const_int 1)] "" - "movm [d2,d3,a2,a3],(sp)" + "* +{ + return \"movm [d2,d3,a2,a3],(sp)\"; +}" [(set_attr "cc" "clobber")]) (define_insn "return" @@ -1369,7 +1408,7 @@ ;; Try to combine consecutive updates of the stack pointer (or any ;; other register for that matter). (define_peephole - [(set (match_operand:SI 0 "register_operand" "=dax") + [(set (match_operand:SI 0 "register_operand" "=dxay") (plus:SI (match_dup 0) (match_operand 1 "const_int_operand" ""))) (set (match_dup 0) @@ -1393,7 +1432,7 @@ ;; This will work on the mn10200 because we can check the ZX flag ;; if the comparison is in HImode. (define_peephole - [(set (cc0) (match_operand:SI 0 "register_operand" "d")) + [(set (cc0) (match_operand:SI 0 "register_operand" "dx")) (set (pc) (if_then_else (ge (cc0) (const_int 0)) (match_operand 1 "" "") (pc)))] @@ -1402,7 +1441,7 @@ [(set_attr "cc" "clobber")]) (define_peephole - [(set (cc0) (match_operand:SI 0 "register_operand" "d")) + [(set (cc0) (match_operand:SI 0 "register_operand" "dx")) (set (pc) (if_then_else (lt (cc0) (const_int 0)) (match_operand 1 "" "") (pc)))] @@ -1411,7 +1450,7 @@ [(set_attr "cc" "clobber")]) (define_peephole - [(set (cc0) (match_operand:SI 0 "register_operand" "d")) + [(set (cc0) (match_operand:SI 0 "register_operand" "dx")) (set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (match_operand 1 "" "")))] @@ -1420,7 +1459,7 @@ [(set_attr "cc" "clobber")]) (define_peephole - [(set (cc0) (match_operand:SI 0 "register_operand" "d")) + [(set (cc0) (match_operand:SI 0 "register_operand" "dx")) (set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (match_operand 1 "" "")))]