From: Lehua Ding Date: Fri, 1 Sep 2023 02:51:43 +0000 (+0800) Subject: RISC-V: Adjust expand_cond_len_{unary,binop,op} api X-Git-Tag: basepoints/gcc-15~6521 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4d1c8b04ec8731b57ddbc80d76e40a61d8fa3324;p=thirdparty%2Fgcc.git RISC-V: Adjust expand_cond_len_{unary,binop,op} api This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code` to `unsigned icode` and use the icode directly to determine whether the rounding_mode operand is required. gcc/ChangeLog: * config/riscv/autovec.md: Adjust. * config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. * config/riscv/riscv-v.cc (needs_fp_rounding): Ditto. (expand_cond_len_op): Ditto. (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. (expand_cond_len_ternop): Ditto. --- diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 2e3e8e720a52..8eed7682311e 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1587,7 +1587,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1624,7 +1625,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1663,7 +1665,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1703,7 +1706,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1743,7 +1747,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1781,7 +1786,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e145ee6c69b3..dd7aa360ec5b 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -426,8 +426,8 @@ bool neg_simm5_p (rtx); bool has_vi_variant_p (rtx_code, rtx); void expand_vec_cmp (rtx, rtx_code, rtx, rtx); bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); -void expand_cond_len_unop (rtx_code, rtx *); -void expand_cond_len_binop (rtx_code, rtx *); +void expand_cond_len_unop (unsigned, rtx *); +void expand_cond_len_binop (unsigned, rtx *); void expand_reduction (rtx_code, rtx *, rtx, reduction_type = reduction_type::UNORDERED); #endif diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c8ad96f44d5e..926d541ec44d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -245,6 +245,12 @@ public: always Pmode. */ if (mode == VOIDmode) mode = Pmode; + else + /* Early assertion ensures same mode since maybe_legitimize_operand + will check this. */ + gcc_assert (GET_MODE (ops[opno]) == VOIDmode + || GET_MODE (ops[opno]) == mode); + add_input_operand (ops[opno], mode); } @@ -291,6 +297,7 @@ public: if (m_insn_flags & FRM_DYN_P) add_rounding_mode_operand (FRM_DYN); + gcc_assert (insn_data[(int) icode].n_operands == m_opno); expand (icode, any_mem_p); } @@ -2948,17 +2955,20 @@ expand_load_store (rtx *ops, bool is_load) /* Return true if the operation is the floating-point operation need FRM. */ static bool -needs_fp_rounding (rtx_code code, machine_mode mode) +needs_fp_rounding (unsigned icode, machine_mode mode) { if (!FLOAT_MODE_P (mode)) return false; - return code != SMIN && code != SMAX && code != NEG && code != ABS; + + return icode != maybe_code_for_pred (SMIN, mode) + && icode != maybe_code_for_pred (SMAX, mode) + && icode != maybe_code_for_pred (NEG, mode) + && icode != maybe_code_for_pred (ABS, mode); } /* Subroutine to expand COND_LEN_* patterns. */ static void -expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, - rtx len) +expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2977,7 +2987,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, else insn_flags |= TU_POLICY_P | MU_POLICY_P; - if (needs_fp_rounding (code, mode)) + if (needs_fp_rounding (icode, mode)) insn_flags |= FRM_DYN_P; if (is_vlmax_len) @@ -2988,7 +2998,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, /* Expand unary ops COND_LEN_*. */ void -expand_cond_len_unop (rtx_code code, rtx *ops) +expand_cond_len_unop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2996,15 +3006,13 @@ expand_cond_len_unop (rtx_code code, rtx *ops) rtx merge = ops[3]; rtx len = ops[4]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src}; - expand_cond_len_op (code, icode, UNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); } /* Expand binary ops COND_LEN_*. */ void -expand_cond_len_binop (rtx_code code, rtx *ops) +expand_cond_len_binop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -3013,10 +3021,8 @@ expand_cond_len_binop (rtx_code code, rtx *ops) rtx merge = ops[4]; rtx len = ops[5]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src1, src2}; - expand_cond_len_op (code, icode, BINARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); } /* Prepare insn_code for gather_load/scatter_store according to @@ -3188,7 +3194,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) rtx len = ops[6]; rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; - expand_cond_len_op (UNSPEC, icode, TERNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); } /* Expand reduction operations. */