From: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed, 22 Nov 2023 01:18:28 +0000 (+0000)
Subject: RISC-V: Implement `riscv_emit_unary' helper
X-Git-Tag: basepoints/gcc-15~4415
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4daeedcbaf5d596d00004ca6ec4835dc57bdd02a;p=thirdparty%2Fgcc.git

RISC-V: Implement `riscv_emit_unary' helper

Add a `riscv_emit_unary' helper for unary operations, complementing
`riscv_emit_binary'.

	gcc/
	* config/riscv/riscv-protos.h (riscv_emit_unary): New prototype.
	* config/riscv/riscv.cc (riscv_emit_unary): New function.
---

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ae528db1898d..0050a8b0edf1 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -134,6 +134,7 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int);
 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0);
 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
+extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x);
 extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
 #endif
 extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4424882ec3a1..5198da6d9360 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1732,6 +1732,14 @@ riscv_emit_set (rtx target, rtx src)
   return target;
 }
 
+/* Emit an instruction of the form (set DEST (CODE X)).  */
+
+rtx
+riscv_emit_unary (enum rtx_code code, rtx dest, rtx x)
+{
+  return riscv_emit_set (dest, gen_rtx_fmt_e (code, GET_MODE (dest), x));
+}
+
 /* Emit an instruction of the form (set DEST (CODE X Y)).  */
 
 rtx