From: Markus Stockhausen Date: Wed, 7 Jan 2026 07:02:40 +0000 (+0100) Subject: realtek: phy: enhance RTL8218B initialization X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4fa90d8;p=thirdparty%2Fopenwrt.git realtek: phy: enhance RTL8218B initialization The RTL8214FC and the RTL8218B share the same register set and need to be initialized quite similar. In the future the RTl8214FC will get its own setup sequence. To keep the codebase small the common parts (serdes & copper) will be covered by the existing RTL8218B configuration. Enhance the RTL8218B setup with this separate commit to ensure that nothing breaks. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/21435 Signed-off-by: Stijn Tintel --- diff --git a/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c index b6d2aba00f3..8ac3024439d 100644 --- a/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c @@ -904,9 +904,19 @@ static int rtl8218b_config_init(struct phy_device *phydev) phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(0, 1), 0x14, 0, BIT(3)); /* magic CMU setting for stable connectivity of first MAC serdes */ phy_write_paged(phydev, 0x462, 0x15, 0x6e58); + /* magic setting for rate select 10G full */ + phy_write_paged(phydev, 0x464, 0x15, 0x202a); + /* magic setting for variable gain amplifier */ + phy_modify_paged(phydev, 0x464, 0x12, 0, 0x1f80); + /* magic setting for equalizer of second MAC serdes */ + phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 8), 0x12, 0x2020); + /* unknown magic for second MAC serdes */ + phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 9), 0x11, 0xc014); rtl8218b_cmu_reset(phydev, 0); for (int sds = 0; sds < 2; sds++) { + /* disable ring PLL for serdes 2+3 */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds + 1, 8), 0x11, BIT(15), 0); /* force negative clock edge */ phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x17, 0, BIT(14)); rtl8218b_cmu_reset(phydev, 5 + sds);