From: zhengnannan <zhengnannan@huawei.com>
Date: Tue, 20 Oct 2020 16:53:04 +0000 (+0100)
Subject: AArch64: Add FLAG for get/set reg intrinsics [PR94442]
X-Git-Tag: basepoints/gcc-12~4126
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4fb0ee84ad8c9b789e2465c85ea048e3320365b0;p=thirdparty%2Fgcc.git

AArch64: Add FLAG for get/set reg intrinsics [PR94442]

2020-10-20  Zhiheng Xie  <xiezhiheng@huawei.com>
	    Nannan Zheng  <zhengnannan@huawei.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
	for get/set reg intrinsics.
---

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 4c23328a5755..5bc596dbffc7 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -70,26 +70,26 @@
   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, ALL)
 
   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
-  BUILTIN_VDC (GETREG, get_dregoi, 0, ALL)
-  BUILTIN_VDC (GETREG, get_dregci, 0, ALL)
-  BUILTIN_VDC (GETREG, get_dregxi, 0, ALL)
-  VAR1 (GETREGP, get_dregoi, 0, ALL, di)
-  VAR1 (GETREGP, get_dregci, 0, ALL, di)
-  VAR1 (GETREGP, get_dregxi, 0, ALL, di)
+  BUILTIN_VDC (GETREG, get_dregoi, 0, AUTO_FP)
+  BUILTIN_VDC (GETREG, get_dregci, 0, AUTO_FP)
+  BUILTIN_VDC (GETREG, get_dregxi, 0, AUTO_FP)
+  VAR1 (GETREGP, get_dregoi, 0, AUTO_FP, di)
+  VAR1 (GETREGP, get_dregci, 0, AUTO_FP, di)
+  VAR1 (GETREGP, get_dregxi, 0, AUTO_FP, di)
   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (GETREG, get_qregoi, 0, ALL)
-  BUILTIN_VQ (GETREG, get_qregci, 0, ALL)
-  BUILTIN_VQ (GETREG, get_qregxi, 0, ALL)
-  VAR1 (GETREGP, get_qregoi, 0, ALL, v2di)
-  VAR1 (GETREGP, get_qregci, 0, ALL, v2di)
-  VAR1 (GETREGP, get_qregxi, 0, ALL, v2di)
+  BUILTIN_VQ (GETREG, get_qregoi, 0, AUTO_FP)
+  BUILTIN_VQ (GETREG, get_qregci, 0, AUTO_FP)
+  BUILTIN_VQ (GETREG, get_qregxi, 0, AUTO_FP)
+  VAR1 (GETREGP, get_qregoi, 0, AUTO_FP, v2di)
+  VAR1 (GETREGP, get_qregci, 0, AUTO_FP, v2di)
+  VAR1 (GETREGP, get_qregxi, 0, AUTO_FP, v2di)
   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (SETREG, set_qregoi, 0, ALL)
-  BUILTIN_VQ (SETREG, set_qregci, 0, ALL)
-  BUILTIN_VQ (SETREG, set_qregxi, 0, ALL)
-  VAR1 (SETREGP, set_qregoi, 0, ALL, v2di)
-  VAR1 (SETREGP, set_qregci, 0, ALL, v2di)
-  VAR1 (SETREGP, set_qregxi, 0, ALL, v2di)
+  BUILTIN_VQ (SETREG, set_qregoi, 0, AUTO_FP)
+  BUILTIN_VQ (SETREG, set_qregci, 0, AUTO_FP)
+  BUILTIN_VQ (SETREG, set_qregxi, 0, AUTO_FP)
+  VAR1 (SETREGP, set_qregoi, 0, AUTO_FP, v2di)
+  VAR1 (SETREGP, set_qregci, 0, AUTO_FP, v2di)
+  VAR1 (SETREGP, set_qregxi, 0, AUTO_FP, v2di)
   /* Implemented by aarch64_ld1x2<VQ:mode>. */
   BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, ALL)
   /* Implemented by aarch64_ld1x2<VDC:mode>. */