From: Andrew Stubbs <ams@codesourcery.com>
Date: Mon, 10 Feb 2020 13:23:29 +0000 (+0000)
Subject: amdgcn: Add fold_left_plus vector reductions
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=50931e513b39f39ce36229443eb6b5795a774c60;p=thirdparty%2Fgcc.git

amdgcn: Add fold_left_plus vector reductions

These aren't real in-order instructions, because the ISA can't do that
quickly, but a means to allow regular out-of-order reductions when that's
good enough, but the middle-end doesn't know so.

	gcc/
	* config/gcn/gcn-valu.md (fold_left_plus_<mode>): New.

(cherry picked from commit bf628a97efaf11204ab02527b30ca71d7759ca37)
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ad94c5140bbd..bf1cd4266f63 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-07-03  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+	* config/gcn/gcn-valu.md (fold_left_plus_<mode>): New.
+
 2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 6d7fecaa12c2..26559ff765e2 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -3076,6 +3076,26 @@
     DONE;
   })
 
+;; Warning: This "-ffast-math" implementation converts in-order reductions
+;;          into associative reductions. It's also used where OpenMP or
+;;          OpenACC paralellization has already broken the in-order semantics.
+(define_expand "fold_left_plus_<mode>"
+ [(match_operand:<SCALAR_MODE> 0 "register_operand")
+  (match_operand:<SCALAR_MODE> 1 "gcn_alu_operand")
+  (match_operand:V_FP 2 "gcn_alu_operand")]
+  "can_create_pseudo_p ()
+   && (flag_openacc || flag_openmp
+       || flag_associative_math)"
+  {
+    rtx dest = operands[0];
+    rtx scalar = operands[1];
+    rtx vector = operands[2];
+    rtx tmp = gen_reg_rtx (<SCALAR_MODE>mode);
+
+    emit_insn (gen_reduc_plus_scal_<mode> (tmp, vector));
+    emit_insn (gen_add<scalar_mode>3 (dest, scalar, tmp));
+     DONE;
+   })
 
 (define_insn "*<reduc_op>_dpp_shr_<mode>"
   [(set (match_operand:V_1REG 0 "register_operand"   "=v")