From: Julian Seward Date: Mon, 28 Mar 2011 12:14:48 +0000 (+0000) Subject: Remove dead assignments that gcc-4.6.0 complains about X-Git-Tag: svn/VALGRIND_3_7_0^2~105 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=50daebf7e344cd3c54259d1b51780e157e75d7eb;p=thirdparty%2Fvalgrind.git Remove dead assignments that gcc-4.6.0 complains about ("[-Wunused-but-set-variable]") git-svn-id: svn://svn.valgrind.org/vex/trunk@2119 --- diff --git a/VEX/priv/guest_arm_helpers.c b/VEX/priv/guest_arm_helpers.c index f6689a0c3d..93f81150d5 100644 --- a/VEX/priv/guest_arm_helpers.c +++ b/VEX/priv/guest_arm_helpers.c @@ -333,12 +333,11 @@ IRExpr* guest_arm_spechelper ( HChar* function_name, if (vex_streq(function_name, "armg_calculate_condition")) { /* specialise calls to above "armg_calculate condition" function */ - IRExpr *cond_n_op, *cc_dep1, *cc_dep2, *cc_dep3; + IRExpr *cond_n_op, *cc_dep1, *cc_dep2; vassert(arity == 4); cond_n_op = args[0]; /* ARMCondcode << 4 | ARMG_CC_OP_* */ cc_dep1 = args[1]; cc_dep2 = args[2]; - cc_dep3 = args[3]; /*---------------- SUB ----------------*/ diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 8076ba1553..696c6cdeab 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -3794,7 +3794,7 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) case 5: if (B == 0) { /* VRSHL */ - IROp op, op_shrn, op_shln, cmp_gt, op_sub, op_add; + IROp op, op_shrn, op_shln, cmp_gt, op_add; IRTemp shval, old_shval, imm_val, round; UInt i; ULong imm; @@ -3814,28 +3814,24 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) switch (size) { case 0: op = Q ? Iop_Shl8x16 : Iop_Shl8x8; - op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; op_add = Q ? Iop_Add8x16 : Iop_Add8x8; op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break; case 1: op = Q ? Iop_Shl16x8 : Iop_Shl16x4; - op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; op_add = Q ? Iop_Add16x8 : Iop_Add16x4; op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break; case 2: op = Q ? Iop_Shl32x4 : Iop_Shl32x2; - op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; op_add = Q ? Iop_Add32x4 : Iop_Add32x2; op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break; case 3: op = Q ? Iop_Shl64x2 : Iop_Shl64; - op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; op_add = Q ? Iop_Add64x2 : Iop_Add64; op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; @@ -3847,28 +3843,24 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) switch (size) { case 0: op = Q ? Iop_Sal8x16 : Iop_Sal8x8; - op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; op_add = Q ? Iop_Add8x16 : Iop_Add8x8; op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break; case 1: op = Q ? Iop_Sal16x8 : Iop_Sal16x4; - op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; op_add = Q ? Iop_Add16x8 : Iop_Add16x4; op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break; case 2: op = Q ? Iop_Sal32x4 : Iop_Sal32x2; - op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; op_add = Q ? Iop_Add32x4 : Iop_Add32x2; op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break; case 3: op = Q ? Iop_Sal64x2 : Iop_Sal64x1; - op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; op_add = Q ? Iop_Add64x2 : Iop_Add64; op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; @@ -3939,7 +3931,7 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) nreg); } else { /* VQRSHL */ - IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt, op_sub, op_add; + IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt, op_add; IRTemp tmp, shval, mask, old_shval, imm_val, round; UInt i; ULong esize, imm; @@ -3960,7 +3952,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) switch (size) { case 0: op = Q ? Iop_QShl8x16 : Iop_QShl8x8; - op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; op_add = Q ? Iop_Add8x16 : Iop_Add8x8; op_rev = Q ? Iop_Shr8x16 : Iop_Shr8x8; op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; @@ -3968,7 +3959,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 1: op = Q ? Iop_QShl16x8 : Iop_QShl16x4; - op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; op_add = Q ? Iop_Add16x8 : Iop_Add16x4; op_rev = Q ? Iop_Shr16x8 : Iop_Shr16x4; op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; @@ -3976,7 +3966,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 2: op = Q ? Iop_QShl32x4 : Iop_QShl32x2; - op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; op_add = Q ? Iop_Add32x4 : Iop_Add32x2; op_rev = Q ? Iop_Shr32x4 : Iop_Shr32x2; op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; @@ -3984,7 +3973,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 3: op = Q ? Iop_QShl64x2 : Iop_QShl64x1; - op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; op_add = Q ? Iop_Add64x2 : Iop_Add64; op_rev = Q ? Iop_Shr64x2 : Iop_Shr64; op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; @@ -3997,7 +3985,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) switch (size) { case 0: op = Q ? Iop_QSal8x16 : Iop_QSal8x8; - op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; op_add = Q ? Iop_Add8x16 : Iop_Add8x8; op_rev = Q ? Iop_Sar8x16 : Iop_Sar8x8; op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; @@ -4005,7 +3992,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 1: op = Q ? Iop_QSal16x8 : Iop_QSal16x4; - op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; op_add = Q ? Iop_Add16x8 : Iop_Add16x4; op_rev = Q ? Iop_Sar16x8 : Iop_Sar16x4; op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; @@ -4013,7 +3999,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 2: op = Q ? Iop_QSal32x4 : Iop_QSal32x2; - op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; op_add = Q ? Iop_Add32x4 : Iop_Add32x2; op_rev = Q ? Iop_Sar32x4 : Iop_Sar32x2; op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; @@ -4021,7 +4006,6 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) break; case 3: op = Q ? Iop_QSal64x2 : Iop_QSal64x1; - op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; op_add = Q ? Iop_Add64x2 : Iop_Add64; op_rev = Q ? Iop_Sar64x2 : Iop_Sar64; op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; @@ -5597,11 +5581,10 @@ Bool dis_neon_data_2reg_and_scalar ( UInt theInstr, IRTemp condT ) if (INSN(11,8) == BITS4(1,0,1,1) && !U) { IROp op ,op2, dup, get; ULong imm; - IRTemp res, arg_m, arg_n; + IRTemp arg_m, arg_n; if (dreg & 1) return False; dreg >>= 1; - res = newTemp(Ity_V128); arg_m = newTemp(Ity_I64); arg_n = newTemp(Ity_I64); assign(arg_n, getDRegI64(nreg)); diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index 4bba9a35de..a2987eea5d 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -5943,7 +5943,6 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch arch_host, HReg hreg, hregHI; ISelEnv* env; UInt hwcaps_host = archinfo_host->hwcaps; - Bool neon = False; static UInt counter = 0; /* sanity ... */ @@ -5981,7 +5980,6 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch arch_host, case Ity_I64: if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { hreg = mkHReg(j++, HRcFlt64, True); - neon = True; } else { hregHI = mkHReg(j++, HRcInt32, True); hreg = mkHReg(j++, HRcInt32, True); @@ -5989,8 +5987,7 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch arch_host, break; case Ity_F32: hreg = mkHReg(j++, HRcFlt32, True); break; case Ity_F64: hreg = mkHReg(j++, HRcFlt64, True); break; - case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); - neon = True; break; + case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); break; default: ppIRType(bb->tyenv->types[i]); vpanic("iselBB: IRTemp type"); } diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index c429c06f22..971043667a 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -5246,11 +5246,7 @@ static UChar * s390_widen_emit(UChar *buf, const s390_insn *insn, UInt from_size, Bool sign_extend) { - s390_opnd_RMI opnd; - UInt dst; - - dst = hregNumber(insn->variant.unop.dst); - opnd = insn->variant.unop.src; + s390_opnd_RMI opnd = insn->variant.unop.src; switch (opnd.tag) { case S390_OPND_REG: { @@ -6093,11 +6089,9 @@ s390_insn_branch_emit(UChar *buf, const s390_insn *insn) { s390_opnd_RMI dst; s390_cc_t cond; - IRJumpKind kind; UInt trc; UChar *p, *ptmp = 0; /* avoid compiler warnings */ - kind = insn->variant.branch.kind; cond = insn->variant.branch.cond; dst = insn->variant.branch.dst;