From: Sasha Levin Date: Sun, 24 Dec 2023 14:10:25 +0000 (-0500) Subject: Fixes for 6.1 X-Git-Tag: v6.1.70~43^2~11 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=50ffd2f3d07a4611e3eccd189c1d47dd840dfeee;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.1 Signed-off-by: Sasha Levin --- diff --git a/queue-6.1/drm-i915-dpt-only-do-the-pot-stride-remap-when-using.patch b/queue-6.1/drm-i915-dpt-only-do-the-pot-stride-remap-when-using.patch new file mode 100644 index 00000000000..1ff424a9873 --- /dev/null +++ b/queue-6.1/drm-i915-dpt-only-do-the-pot-stride-remap-when-using.patch @@ -0,0 +1,41 @@ +From ef2b3ae3fa3283fd1ad101a17faf8fb24f6e10db Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 11:05:18 +0200 +Subject: drm/i915/dpt: Only do the POT stride remap when using DPT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit ef5cb493a9acd7d97870d6e542020980ae3f3483 ] + +If we want to test with DPT disabled on ADL the POT stride remap +stuff needs to be disabled. Make it depend on actual DPT usage +instead of just assuming it based on the modifier. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230320090522.9909-3-ville.syrjala@linux.intel.com +Reviewed-by: Juha-Pekka Heikkila +Stable-dep-of: 324b70e997aa ("drm/i915: Fix ADL+ tiled plane stride when the POT stride is smaller than the original") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_fb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c +index 23d854bd73b77..c22ca36a38a9d 100644 +--- a/drivers/gpu/drm/i915/display/intel_fb.c ++++ b/drivers/gpu/drm/i915/display/intel_fb.c +@@ -1176,7 +1176,7 @@ bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) + { + struct drm_i915_private *i915 = to_i915(fb->base.dev); + +- return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR; ++ return IS_ALDERLAKE_P(i915) && intel_fb_uses_dpt(&fb->base); + } + + static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) +-- +2.43.0 + diff --git a/queue-6.1/drm-i915-fix-adl-tiled-plane-stride-when-the-pot-str.patch b/queue-6.1/drm-i915-fix-adl-tiled-plane-stride-when-the-pot-str.patch new file mode 100644 index 00000000000..9ab54fbe7a3 --- /dev/null +++ b/queue-6.1/drm-i915-fix-adl-tiled-plane-stride-when-the-pot-str.patch @@ -0,0 +1,60 @@ +From 57d9d32b7f7a1640d4463e999c4204c00c821ba1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 22:24:43 +0200 +Subject: drm/i915: Fix ADL+ tiled plane stride when the POT stride is smaller + than the original +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit 324b70e997aab0a7deab8cb90711faccda4e98c8 ] + +plane_view_scanout_stride() currently assumes that we had to pad the +mapping stride with dummy pages in order to align it. But that is not +the case if the original fb stride exceeds the aligned stride used +to populate the remapped view, which is calculated from the user +specified framebuffer width rather than the user specified framebuffer +stride. + +Ignore the original fb stride in this case and just stick to the POT +aligned stride. Getting this wrong will cause the plane to fetch the +wrong data, and can lead to fault errors if the page tables at the +bogus location aren't even populated. + +TODO: figure out if this is OK for CCS, or if we should instead increase +the width of the view to cover the entire user specified fb stride +instead... + +Cc: Imre Deak +Cc: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231204202443.31247-1-ville.syrjala@linux.intel.com +Reviewed-by: Imre Deak +Reviewed-by: Juha-Pekka Heikkila +(cherry picked from commit 01a39f1c4f1220a4e6a25729fae87ff5794cbc52) +Cc: stable@vger.kernel.org +Signed-off-by: Jani Nikula +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_fb.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c +index 583b3c0f96ddc..c69a638796c62 100644 +--- a/drivers/gpu/drm/i915/display/intel_fb.c ++++ b/drivers/gpu/drm/i915/display/intel_fb.c +@@ -1316,7 +1316,8 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, + struct drm_i915_private *i915 = to_i915(fb->base.dev); + unsigned int stride_tiles; + +- if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) ++ if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && ++ src_stride_tiles < dst_stride_tiles) + stride_tiles = src_stride_tiles; + else + stride_tiles = dst_stride_tiles; +-- +2.43.0 + diff --git a/queue-6.1/drm-i915-fix-intel_atomic_setup_scalers-plane_state-.patch b/queue-6.1/drm-i915-fix-intel_atomic_setup_scalers-plane_state-.patch new file mode 100644 index 00000000000..561655e3bd2 --- /dev/null +++ b/queue-6.1/drm-i915-fix-intel_atomic_setup_scalers-plane_state-.patch @@ -0,0 +1,62 @@ +From c1cd9a61fc16fd3135cea0c98e23df3181ee26a9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Dec 2023 21:34:34 +0200 +Subject: drm/i915: Fix intel_atomic_setup_scalers() plane_state handling +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit c3070f080f9ba18dea92eaa21730f7ab85b5c8f4 ] + +Since the plane_state variable is declared outside the scaler_users +loop in intel_atomic_setup_scalers(), and it's never reset back to +NULL inside the loop we may end up calling intel_atomic_setup_scaler() +with a non-NULL plane state for the pipe scaling case. That is bad +because intel_atomic_setup_scaler() determines whether we are doing +plane scaling or pipe scaling based on plane_state!=NULL. The end +result is that we may miscalculate the scaler mode for pipe scaling. + +The hardware becomes somewhat upset if we end up in this situation +when scanning out a planar format on a SDR plane. We end up +programming the pipe scaler into planar mode as well, and the +result is a screenfull of garbage. + +Fix the situation by making sure we pass the correct plane_state==NULL +when calculating the scaler mode for pipe scaling. + +Cc: stable@vger.kernel.org +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231207193441.20206-2-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit e81144106e21271c619f0c722a09e27ccb8c043d) +Signed-off-by: Jani Nikula +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/skl_scaler.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c +index 83a61efa84395..0b74f91e865d0 100644 +--- a/drivers/gpu/drm/i915/display/skl_scaler.c ++++ b/drivers/gpu/drm/i915/display/skl_scaler.c +@@ -493,7 +493,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, + { + struct drm_plane *plane = NULL; + struct intel_plane *intel_plane; +- struct intel_plane_state *plane_state = NULL; + struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_atomic_state *drm_state = crtc_state->uapi.state; +@@ -525,6 +524,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, + + /* walkthrough scaler_users bits and start assigning scalers */ + for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { ++ struct intel_plane_state *plane_state = NULL; + int *scaler_id; + const char *name; + int idx, ret; +-- +2.43.0 + diff --git a/queue-6.1/drm-i915-mtl-add-mtl-for-remapping-ccs-fbs.patch b/queue-6.1/drm-i915-mtl-add-mtl-for-remapping-ccs-fbs.patch new file mode 100644 index 00000000000..d399b12667a --- /dev/null +++ b/queue-6.1/drm-i915-mtl-add-mtl-for-remapping-ccs-fbs.patch @@ -0,0 +1,63 @@ +From ce63ebc3871c0c4de9b03e0d656cd4bd9a292721 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 May 2023 16:40:05 +0200 +Subject: drm/i915/mtl: Add MTL for remapping CCS FBs + +From: Clint Taylor + +[ Upstream commit 0da6bfe857ea9399498876cbe6ef428637b6e475 ] + +Add support for remapping CCS FBs on MTL to remove the restriction +of the power-of-two sized stride and the 2MB surface offset alignment +for these FBs. + +Signed-off-by: Clint Taylor +Signed-off-by: Juha-Pekka Heikkila +Reviewed-by: Radhakrishna Sripada +Signed-off-by: Nirmoy Das +Link: https://patchwork.freedesktop.org/patch/msgid/20230505144005.23480-2-nirmoy.das@intel.com +Stable-dep-of: 324b70e997aa ("drm/i915: Fix ADL+ tiled plane stride when the POT stride is smaller than the original") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_fb.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c +index c22ca36a38a9d..583b3c0f96ddc 100644 +--- a/drivers/gpu/drm/i915/display/intel_fb.c ++++ b/drivers/gpu/drm/i915/display/intel_fb.c +@@ -1176,7 +1176,8 @@ bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) + { + struct drm_i915_private *i915 = to_i915(fb->base.dev); + +- return IS_ALDERLAKE_P(i915) && intel_fb_uses_dpt(&fb->base); ++ return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && ++ intel_fb_uses_dpt(&fb->base); + } + + static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) +@@ -1312,9 +1313,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, + unsigned int tile_width, + unsigned int src_stride_tiles, unsigned int dst_stride_tiles) + { ++ struct drm_i915_private *i915 = to_i915(fb->base.dev); + unsigned int stride_tiles; + +- if (IS_ALDERLAKE_P(to_i915(fb->base.dev))) ++ if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) + stride_tiles = src_stride_tiles; + else + stride_tiles = dst_stride_tiles; +@@ -1520,7 +1522,8 @@ static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_vi + memset(view, 0, sizeof(*view)); + view->gtt.type = view_type; + +- if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915)) ++ if (view_type == I915_GTT_VIEW_REMAPPED && ++ (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) + view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-i915-mtl-limit-second-scaler-vertical-scaling-in.patch b/queue-6.1/drm-i915-mtl-limit-second-scaler-vertical-scaling-in.patch new file mode 100644 index 00000000000..bde8a79f028 --- /dev/null +++ b/queue-6.1/drm-i915-mtl-limit-second-scaler-vertical-scaling-in.patch @@ -0,0 +1,170 @@ +From 877feb15a17353699d35bd7ff45dca84a75f115c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Dec 2022 15:05:08 +0200 +Subject: drm/i915/mtl: limit second scaler vertical scaling in ver >= 14 + +From: Luca Coelho + +[ Upstream commit 8d4312e2b228ba7a5ac79154458098274ec61e9b ] + +In newer hardware versions (i.e. display version >= 14), the second +scaler doesn't support vertical scaling. + +The current implementation of the scaling limits is simplified and +only occurs when the planes are created, so we don't know which scaler +is being used. + +In order to handle separate scaling limits for horizontal and vertical +scaling, and different limits per scaler, split the checks in two +phases. We first do a simple check during plane creation and use the +best-case scenario (because we don't know the scaler that may be used +at a later point) and then do a more specific check when the scalers +are actually being set up. + +Signed-off-by: Luca Coelho +Reviewed-by: Stanislav Lisovskiy +Signed-off-by: Radhakrishna Sripada +Link: https://patchwork.freedesktop.org/patch/msgid/20221223130509.43245-2-luciano.coelho@intel.com +Stable-dep-of: c3070f080f9b ("drm/i915: Fix intel_atomic_setup_scalers() plane_state handling") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++--- + 1 file changed, 75 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c +index 18f0a5ae3bacd..61dda54d68e0a 100644 +--- a/drivers/gpu/drm/i915/display/intel_atomic.c ++++ b/drivers/gpu/drm/i915/display/intel_atomic.c +@@ -41,6 +41,7 @@ + #include "intel_global_state.h" + #include "intel_hdcp.h" + #include "intel_psr.h" ++#include "intel_fb.h" + #include "skl_universal_plane.h" + + /** +@@ -302,11 +303,11 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, + kfree(crtc_state); + } + +-static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, +- int num_scalers_need, struct intel_crtc *intel_crtc, +- const char *name, int idx, +- struct intel_plane_state *plane_state, +- int *scaler_id) ++static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, ++ int num_scalers_need, struct intel_crtc *intel_crtc, ++ const char *name, int idx, ++ struct intel_plane_state *plane_state, ++ int *scaler_id) + { + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + int j; +@@ -326,7 +327,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta + + if (drm_WARN(&dev_priv->drm, *scaler_id < 0, + "Cannot find scaler for %s:%d\n", name, idx)) +- return; ++ return -EINVAL; + + /* set scaler mode */ + if (plane_state && plane_state->hw.fb && +@@ -367,9 +368,71 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta + mode = SKL_PS_SCALER_MODE_DYN; + } + ++ /* ++ * FIXME: we should also check the scaler factors for pfit, so ++ * this shouldn't be tied directly to planes. ++ */ ++ if (plane_state && plane_state->hw.fb) { ++ const struct drm_framebuffer *fb = plane_state->hw.fb; ++ const struct drm_rect *src = &plane_state->uapi.src; ++ const struct drm_rect *dst = &plane_state->uapi.dst; ++ int hscale, vscale, max_vscale, max_hscale; ++ ++ /* ++ * FIXME: When two scalers are needed, but only one of ++ * them needs to downscale, we should make sure that ++ * the one that needs downscaling support is assigned ++ * as the first scaler, so we don't reject downscaling ++ * unnecessarily. ++ */ ++ ++ if (DISPLAY_VER(dev_priv) >= 14) { ++ /* ++ * On versions 14 and up, only the first ++ * scaler supports a vertical scaling factor ++ * of more than 1.0, while a horizontal ++ * scaling factor of 3.0 is supported. ++ */ ++ max_hscale = 0x30000 - 1; ++ if (*scaler_id == 0) ++ max_vscale = 0x30000 - 1; ++ else ++ max_vscale = 0x10000; ++ ++ } else if (DISPLAY_VER(dev_priv) >= 10 || ++ !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { ++ max_hscale = 0x30000 - 1; ++ max_vscale = 0x30000 - 1; ++ } else { ++ max_hscale = 0x20000 - 1; ++ max_vscale = 0x20000 - 1; ++ } ++ ++ /* ++ * FIXME: We should change the if-else block above to ++ * support HQ vs dynamic scaler properly. ++ */ ++ ++ /* Check if required scaling is within limits */ ++ hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale); ++ vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); ++ ++ if (hscale < 0 || vscale < 0) { ++ drm_dbg_kms(&dev_priv->drm, ++ "Scaler %d doesn't support required plane scaling\n", ++ *scaler_id); ++ drm_rect_debug_print("src: ", src, true); ++ drm_rect_debug_print("dst: ", dst, false); ++ ++ return -EINVAL; ++ } ++ } ++ + drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", + intel_crtc->pipe, *scaler_id, name, idx); + scaler_state->scalers[*scaler_id].mode = mode; ++ ++ return 0; + } + + /** +@@ -429,7 +492,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, + for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { + int *scaler_id; + const char *name; +- int idx; ++ int idx, ret; + + /* skip if scaler not required */ + if (!(scaler_state->scaler_users & (1 << i))) +@@ -486,9 +549,11 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, + scaler_id = &plane_state->scaler_id; + } + +- intel_atomic_setup_scaler(scaler_state, num_scalers_need, +- intel_crtc, name, idx, +- plane_state, scaler_id); ++ ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, ++ intel_crtc, name, idx, ++ plane_state, scaler_id); ++ if (ret < 0) ++ return ret; + } + + return 0; +-- +2.43.0 + diff --git a/queue-6.1/drm-i915-relocate-intel_atomic_setup_scalers.patch b/queue-6.1/drm-i915-relocate-intel_atomic_setup_scalers.patch new file mode 100644 index 00000000000..adbd8cf3775 --- /dev/null +++ b/queue-6.1/drm-i915-relocate-intel_atomic_setup_scalers.patch @@ -0,0 +1,613 @@ +From 46395ae5d99059a0a311608606ed3f228ae2d6e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 18 Apr 2023 20:55:16 +0300 +Subject: drm/i915: Relocate intel_atomic_setup_scalers() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit 8976b18249407df8bf6ea18ecae0640a15341a50 ] + +Move intel_atomic_setup_scalers() next to the other scaler +code in skl_scaler.c. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-4-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +Stable-dep-of: c3070f080f9b ("drm/i915: Fix intel_atomic_setup_scalers() plane_state handling") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_atomic.c | 256 ------------------- + drivers/gpu/drm/i915/display/intel_atomic.h | 4 - + drivers/gpu/drm/i915/display/skl_scaler.c | 257 ++++++++++++++++++++ + drivers/gpu/drm/i915/display/skl_scaler.h | 10 +- + 4 files changed, 265 insertions(+), 262 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c +index 61dda54d68e0a..a502af0b6dd47 100644 +--- a/drivers/gpu/drm/i915/display/intel_atomic.c ++++ b/drivers/gpu/drm/i915/display/intel_atomic.c +@@ -303,262 +303,6 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, + kfree(crtc_state); + } + +-static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, +- int num_scalers_need, struct intel_crtc *intel_crtc, +- const char *name, int idx, +- struct intel_plane_state *plane_state, +- int *scaler_id) +-{ +- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); +- int j; +- u32 mode; +- +- if (*scaler_id < 0) { +- /* find a free scaler */ +- for (j = 0; j < intel_crtc->num_scalers; j++) { +- if (scaler_state->scalers[j].in_use) +- continue; +- +- *scaler_id = j; +- scaler_state->scalers[*scaler_id].in_use = 1; +- break; +- } +- } +- +- if (drm_WARN(&dev_priv->drm, *scaler_id < 0, +- "Cannot find scaler for %s:%d\n", name, idx)) +- return -EINVAL; +- +- /* set scaler mode */ +- if (plane_state && plane_state->hw.fb && +- plane_state->hw.fb->format->is_yuv && +- plane_state->hw.fb->format->num_planes > 1) { +- struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); +- if (DISPLAY_VER(dev_priv) == 9) { +- mode = SKL_PS_SCALER_MODE_NV12; +- } else if (icl_is_hdr_plane(dev_priv, plane->id)) { +- /* +- * On gen11+'s HDR planes we only use the scaler for +- * scaling. They have a dedicated chroma upsampler, so +- * we don't need the scaler to upsample the UV plane. +- */ +- mode = PS_SCALER_MODE_NORMAL; +- } else { +- struct intel_plane *linked = +- plane_state->planar_linked_plane; +- +- mode = PS_SCALER_MODE_PLANAR; +- +- if (linked) +- mode |= PS_PLANE_Y_SEL(linked->id); +- } +- } else if (DISPLAY_VER(dev_priv) >= 10) { +- mode = PS_SCALER_MODE_NORMAL; +- } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { +- /* +- * when only 1 scaler is in use on a pipe with 2 scalers +- * scaler 0 operates in high quality (HQ) mode. +- * In this case use scaler 0 to take advantage of HQ mode +- */ +- scaler_state->scalers[*scaler_id].in_use = 0; +- *scaler_id = 0; +- scaler_state->scalers[0].in_use = 1; +- mode = SKL_PS_SCALER_MODE_HQ; +- } else { +- mode = SKL_PS_SCALER_MODE_DYN; +- } +- +- /* +- * FIXME: we should also check the scaler factors for pfit, so +- * this shouldn't be tied directly to planes. +- */ +- if (plane_state && plane_state->hw.fb) { +- const struct drm_framebuffer *fb = plane_state->hw.fb; +- const struct drm_rect *src = &plane_state->uapi.src; +- const struct drm_rect *dst = &plane_state->uapi.dst; +- int hscale, vscale, max_vscale, max_hscale; +- +- /* +- * FIXME: When two scalers are needed, but only one of +- * them needs to downscale, we should make sure that +- * the one that needs downscaling support is assigned +- * as the first scaler, so we don't reject downscaling +- * unnecessarily. +- */ +- +- if (DISPLAY_VER(dev_priv) >= 14) { +- /* +- * On versions 14 and up, only the first +- * scaler supports a vertical scaling factor +- * of more than 1.0, while a horizontal +- * scaling factor of 3.0 is supported. +- */ +- max_hscale = 0x30000 - 1; +- if (*scaler_id == 0) +- max_vscale = 0x30000 - 1; +- else +- max_vscale = 0x10000; +- +- } else if (DISPLAY_VER(dev_priv) >= 10 || +- !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { +- max_hscale = 0x30000 - 1; +- max_vscale = 0x30000 - 1; +- } else { +- max_hscale = 0x20000 - 1; +- max_vscale = 0x20000 - 1; +- } +- +- /* +- * FIXME: We should change the if-else block above to +- * support HQ vs dynamic scaler properly. +- */ +- +- /* Check if required scaling is within limits */ +- hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale); +- vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); +- +- if (hscale < 0 || vscale < 0) { +- drm_dbg_kms(&dev_priv->drm, +- "Scaler %d doesn't support required plane scaling\n", +- *scaler_id); +- drm_rect_debug_print("src: ", src, true); +- drm_rect_debug_print("dst: ", dst, false); +- +- return -EINVAL; +- } +- } +- +- drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", +- intel_crtc->pipe, *scaler_id, name, idx); +- scaler_state->scalers[*scaler_id].mode = mode; +- +- return 0; +-} +- +-/** +- * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests +- * @dev_priv: i915 device +- * @intel_crtc: intel crtc +- * @crtc_state: incoming crtc_state to validate and setup scalers +- * +- * This function sets up scalers based on staged scaling requests for +- * a @crtc and its planes. It is called from crtc level check path. If request +- * is a supportable request, it attaches scalers to requested planes and crtc. +- * +- * This function takes into account the current scaler(s) in use by any planes +- * not being part of this atomic state +- * +- * Returns: +- * 0 - scalers were setup succesfully +- * error code - otherwise +- */ +-int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, +- struct intel_crtc *intel_crtc, +- struct intel_crtc_state *crtc_state) +-{ +- struct drm_plane *plane = NULL; +- struct intel_plane *intel_plane; +- struct intel_plane_state *plane_state = NULL; +- struct intel_crtc_scaler_state *scaler_state = +- &crtc_state->scaler_state; +- struct drm_atomic_state *drm_state = crtc_state->uapi.state; +- struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); +- int num_scalers_need; +- int i; +- +- num_scalers_need = hweight32(scaler_state->scaler_users); +- +- /* +- * High level flow: +- * - staged scaler requests are already in scaler_state->scaler_users +- * - check whether staged scaling requests can be supported +- * - add planes using scalers that aren't in current transaction +- * - assign scalers to requested users +- * - as part of plane commit, scalers will be committed +- * (i.e., either attached or detached) to respective planes in hw +- * - as part of crtc_commit, scaler will be either attached or detached +- * to crtc in hw +- */ +- +- /* fail if required scalers > available scalers */ +- if (num_scalers_need > intel_crtc->num_scalers){ +- drm_dbg_kms(&dev_priv->drm, +- "Too many scaling requests %d > %d\n", +- num_scalers_need, intel_crtc->num_scalers); +- return -EINVAL; +- } +- +- /* walkthrough scaler_users bits and start assigning scalers */ +- for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { +- int *scaler_id; +- const char *name; +- int idx, ret; +- +- /* skip if scaler not required */ +- if (!(scaler_state->scaler_users & (1 << i))) +- continue; +- +- if (i == SKL_CRTC_INDEX) { +- name = "CRTC"; +- idx = intel_crtc->base.base.id; +- +- /* panel fitter case: assign as a crtc scaler */ +- scaler_id = &scaler_state->scaler_id; +- } else { +- name = "PLANE"; +- +- /* plane scaler case: assign as a plane scaler */ +- /* find the plane that set the bit as scaler_user */ +- plane = drm_state->planes[i].ptr; +- +- /* +- * to enable/disable hq mode, add planes that are using scaler +- * into this transaction +- */ +- if (!plane) { +- struct drm_plane_state *state; +- +- /* +- * GLK+ scalers don't have a HQ mode so it +- * isn't necessary to change between HQ and dyn mode +- * on those platforms. +- */ +- if (DISPLAY_VER(dev_priv) >= 10) +- continue; +- +- plane = drm_plane_from_index(&dev_priv->drm, i); +- state = drm_atomic_get_plane_state(drm_state, plane); +- if (IS_ERR(state)) { +- drm_dbg_kms(&dev_priv->drm, +- "Failed to add [PLANE:%d] to drm_state\n", +- plane->base.id); +- return PTR_ERR(state); +- } +- } +- +- intel_plane = to_intel_plane(plane); +- idx = plane->base.id; +- +- /* plane on different crtc cannot be a scaler user of this crtc */ +- if (drm_WARN_ON(&dev_priv->drm, +- intel_plane->pipe != intel_crtc->pipe)) +- continue; +- +- plane_state = intel_atomic_get_new_plane_state(intel_state, +- intel_plane); +- scaler_id = &plane_state->scaler_id; +- } +- +- ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, +- intel_crtc, name, idx, +- plane_state, scaler_id); +- if (ret < 0) +- return ret; +- } +- +- return 0; +-} +- + struct drm_atomic_state * + intel_atomic_state_alloc(struct drm_device *dev) + { +diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h +index 1dc439983dd94..e506f6a873447 100644 +--- a/drivers/gpu/drm/i915/display/intel_atomic.h ++++ b/drivers/gpu/drm/i915/display/intel_atomic.h +@@ -52,8 +52,4 @@ struct intel_crtc_state * + intel_atomic_get_crtc_state(struct drm_atomic_state *state, + struct intel_crtc *crtc); + +-int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, +- struct intel_crtc *intel_crtc, +- struct intel_crtc_state *crtc_state); +- + #endif /* __INTEL_ATOMIC_H__ */ +diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c +index 90f42f63128ec..83a61efa84395 100644 +--- a/drivers/gpu/drm/i915/display/skl_scaler.c ++++ b/drivers/gpu/drm/i915/display/skl_scaler.c +@@ -337,6 +337,263 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, + return 0; + } + ++static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, ++ int num_scalers_need, struct intel_crtc *intel_crtc, ++ const char *name, int idx, ++ struct intel_plane_state *plane_state, ++ int *scaler_id) ++{ ++ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); ++ int j; ++ u32 mode; ++ ++ if (*scaler_id < 0) { ++ /* find a free scaler */ ++ for (j = 0; j < intel_crtc->num_scalers; j++) { ++ if (scaler_state->scalers[j].in_use) ++ continue; ++ ++ *scaler_id = j; ++ scaler_state->scalers[*scaler_id].in_use = 1; ++ break; ++ } ++ } ++ ++ if (drm_WARN(&dev_priv->drm, *scaler_id < 0, ++ "Cannot find scaler for %s:%d\n", name, idx)) ++ return -EINVAL; ++ ++ /* set scaler mode */ ++ if (plane_state && plane_state->hw.fb && ++ plane_state->hw.fb->format->is_yuv && ++ plane_state->hw.fb->format->num_planes > 1) { ++ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); ++ ++ if (DISPLAY_VER(dev_priv) == 9) { ++ mode = SKL_PS_SCALER_MODE_NV12; ++ } else if (icl_is_hdr_plane(dev_priv, plane->id)) { ++ /* ++ * On gen11+'s HDR planes we only use the scaler for ++ * scaling. They have a dedicated chroma upsampler, so ++ * we don't need the scaler to upsample the UV plane. ++ */ ++ mode = PS_SCALER_MODE_NORMAL; ++ } else { ++ struct intel_plane *linked = ++ plane_state->planar_linked_plane; ++ ++ mode = PS_SCALER_MODE_PLANAR; ++ ++ if (linked) ++ mode |= PS_PLANE_Y_SEL(linked->id); ++ } ++ } else if (DISPLAY_VER(dev_priv) >= 10) { ++ mode = PS_SCALER_MODE_NORMAL; ++ } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { ++ /* ++ * when only 1 scaler is in use on a pipe with 2 scalers ++ * scaler 0 operates in high quality (HQ) mode. ++ * In this case use scaler 0 to take advantage of HQ mode ++ */ ++ scaler_state->scalers[*scaler_id].in_use = 0; ++ *scaler_id = 0; ++ scaler_state->scalers[0].in_use = 1; ++ mode = SKL_PS_SCALER_MODE_HQ; ++ } else { ++ mode = SKL_PS_SCALER_MODE_DYN; ++ } ++ ++ /* ++ * FIXME: we should also check the scaler factors for pfit, so ++ * this shouldn't be tied directly to planes. ++ */ ++ if (plane_state && plane_state->hw.fb) { ++ const struct drm_framebuffer *fb = plane_state->hw.fb; ++ const struct drm_rect *src = &plane_state->uapi.src; ++ const struct drm_rect *dst = &plane_state->uapi.dst; ++ int hscale, vscale, max_vscale, max_hscale; ++ ++ /* ++ * FIXME: When two scalers are needed, but only one of ++ * them needs to downscale, we should make sure that ++ * the one that needs downscaling support is assigned ++ * as the first scaler, so we don't reject downscaling ++ * unnecessarily. ++ */ ++ ++ if (DISPLAY_VER(dev_priv) >= 14) { ++ /* ++ * On versions 14 and up, only the first ++ * scaler supports a vertical scaling factor ++ * of more than 1.0, while a horizontal ++ * scaling factor of 3.0 is supported. ++ */ ++ max_hscale = 0x30000 - 1; ++ if (*scaler_id == 0) ++ max_vscale = 0x30000 - 1; ++ else ++ max_vscale = 0x10000; ++ ++ } else if (DISPLAY_VER(dev_priv) >= 10 || ++ !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { ++ max_hscale = 0x30000 - 1; ++ max_vscale = 0x30000 - 1; ++ } else { ++ max_hscale = 0x20000 - 1; ++ max_vscale = 0x20000 - 1; ++ } ++ ++ /* ++ * FIXME: We should change the if-else block above to ++ * support HQ vs dynamic scaler properly. ++ */ ++ ++ /* Check if required scaling is within limits */ ++ hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale); ++ vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); ++ ++ if (hscale < 0 || vscale < 0) { ++ drm_dbg_kms(&dev_priv->drm, ++ "Scaler %d doesn't support required plane scaling\n", ++ *scaler_id); ++ drm_rect_debug_print("src: ", src, true); ++ drm_rect_debug_print("dst: ", dst, false); ++ ++ return -EINVAL; ++ } ++ } ++ ++ drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", ++ intel_crtc->pipe, *scaler_id, name, idx); ++ scaler_state->scalers[*scaler_id].mode = mode; ++ ++ return 0; ++} ++ ++/** ++ * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests ++ * @dev_priv: i915 device ++ * @intel_crtc: intel crtc ++ * @crtc_state: incoming crtc_state to validate and setup scalers ++ * ++ * This function sets up scalers based on staged scaling requests for ++ * a @crtc and its planes. It is called from crtc level check path. If request ++ * is a supportable request, it attaches scalers to requested planes and crtc. ++ * ++ * This function takes into account the current scaler(s) in use by any planes ++ * not being part of this atomic state ++ * ++ * Returns: ++ * 0 - scalers were setup successfully ++ * error code - otherwise ++ */ ++int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, ++ struct intel_crtc *intel_crtc, ++ struct intel_crtc_state *crtc_state) ++{ ++ struct drm_plane *plane = NULL; ++ struct intel_plane *intel_plane; ++ struct intel_plane_state *plane_state = NULL; ++ struct intel_crtc_scaler_state *scaler_state = ++ &crtc_state->scaler_state; ++ struct drm_atomic_state *drm_state = crtc_state->uapi.state; ++ struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); ++ int num_scalers_need; ++ int i; ++ ++ num_scalers_need = hweight32(scaler_state->scaler_users); ++ ++ /* ++ * High level flow: ++ * - staged scaler requests are already in scaler_state->scaler_users ++ * - check whether staged scaling requests can be supported ++ * - add planes using scalers that aren't in current transaction ++ * - assign scalers to requested users ++ * - as part of plane commit, scalers will be committed ++ * (i.e., either attached or detached) to respective planes in hw ++ * - as part of crtc_commit, scaler will be either attached or detached ++ * to crtc in hw ++ */ ++ ++ /* fail if required scalers > available scalers */ ++ if (num_scalers_need > intel_crtc->num_scalers) { ++ drm_dbg_kms(&dev_priv->drm, ++ "Too many scaling requests %d > %d\n", ++ num_scalers_need, intel_crtc->num_scalers); ++ return -EINVAL; ++ } ++ ++ /* walkthrough scaler_users bits and start assigning scalers */ ++ for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { ++ int *scaler_id; ++ const char *name; ++ int idx, ret; ++ ++ /* skip if scaler not required */ ++ if (!(scaler_state->scaler_users & (1 << i))) ++ continue; ++ ++ if (i == SKL_CRTC_INDEX) { ++ name = "CRTC"; ++ idx = intel_crtc->base.base.id; ++ ++ /* panel fitter case: assign as a crtc scaler */ ++ scaler_id = &scaler_state->scaler_id; ++ } else { ++ name = "PLANE"; ++ ++ /* plane scaler case: assign as a plane scaler */ ++ /* find the plane that set the bit as scaler_user */ ++ plane = drm_state->planes[i].ptr; ++ ++ /* ++ * to enable/disable hq mode, add planes that are using scaler ++ * into this transaction ++ */ ++ if (!plane) { ++ struct drm_plane_state *state; ++ ++ /* ++ * GLK+ scalers don't have a HQ mode so it ++ * isn't necessary to change between HQ and dyn mode ++ * on those platforms. ++ */ ++ if (DISPLAY_VER(dev_priv) >= 10) ++ continue; ++ ++ plane = drm_plane_from_index(&dev_priv->drm, i); ++ state = drm_atomic_get_plane_state(drm_state, plane); ++ if (IS_ERR(state)) { ++ drm_dbg_kms(&dev_priv->drm, ++ "Failed to add [PLANE:%d] to drm_state\n", ++ plane->base.id); ++ return PTR_ERR(state); ++ } ++ } ++ ++ intel_plane = to_intel_plane(plane); ++ idx = plane->base.id; ++ ++ /* plane on different crtc cannot be a scaler user of this crtc */ ++ if (drm_WARN_ON(&dev_priv->drm, ++ intel_plane->pipe != intel_crtc->pipe)) ++ continue; ++ ++ plane_state = intel_atomic_get_new_plane_state(intel_state, ++ intel_plane); ++ scaler_id = &plane_state->scaler_id; ++ } ++ ++ ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, ++ intel_crtc, name, idx, ++ plane_state, scaler_id); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int glk_coef_tap(int i) + { + return i % 7; +diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h +index 0097d5d08e102..f040f6ac061f2 100644 +--- a/drivers/gpu/drm/i915/display/skl_scaler.h ++++ b/drivers/gpu/drm/i915/display/skl_scaler.h +@@ -8,17 +8,22 @@ + #include + + enum drm_scaling_filter; ++enum pipe; + struct drm_i915_private; ++struct intel_crtc; + struct intel_crtc_state; +-struct intel_plane_state; + struct intel_plane; +-enum pipe; ++struct intel_plane_state; + + int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); + + int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, + struct intel_plane_state *plane_state); + ++int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, ++ struct intel_crtc *intel_crtc, ++ struct intel_crtc_state *crtc_state); ++ + void skl_pfit_enable(const struct intel_crtc_state *crtc_state); + + void skl_program_plane_scaler(struct intel_plane *plane, +@@ -26,4 +31,5 @@ void skl_program_plane_scaler(struct intel_plane *plane, + const struct intel_plane_state *plane_state); + void skl_detach_scalers(const struct intel_crtc_state *crtc_state); + void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); ++ + #endif +-- +2.43.0 + diff --git a/queue-6.1/nvme-pci-fix-sleeping-function-called-from-interrupt.patch b/queue-6.1/nvme-pci-fix-sleeping-function-called-from-interrupt.patch new file mode 100644 index 00000000000..44ca4391371 --- /dev/null +++ b/queue-6.1/nvme-pci-fix-sleeping-function-called-from-interrupt.patch @@ -0,0 +1,60 @@ +From 0f24a964e3f7e57d3009d8a424fe61ea35de0466 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 17:48:23 +0100 +Subject: nvme-pci: fix sleeping function called from interrupt context + +From: Maurizio Lombardi + +[ Upstream commit f6fe0b2d35457c10ec37acc209d19726bdc16dbd ] + +the nvme_handle_cqe() interrupt handler calls nvme_complete_async_event() +but the latter may call nvme_auth_stop() which is a blocking function. +Sleeping functions can't be called in interrupt context + + BUG: sleeping function called from invalid context + in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 0, name: swapper/15 + Call Trace: + + __cancel_work_timer+0x31e/0x460 + ? nvme_change_ctrl_state+0xcf/0x3c0 [nvme_core] + ? nvme_change_ctrl_state+0xcf/0x3c0 [nvme_core] + nvme_complete_async_event+0x365/0x480 [nvme_core] + nvme_poll_cq+0x262/0xe50 [nvme] + +Fix the bug by moving nvme_auth_stop() to fw_act_work +(executed by the nvme_wq workqueue) + +Fixes: f50fff73d620 ("nvme: implement In-Band authentication") +Signed-off-by: Maurizio Lombardi +Reviewed-by: Jens Axboe +Reviewed-by: Sagi Grimberg +Signed-off-by: Keith Busch +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c +index eb7c87b344b8f..5b906dbb1096c 100644 +--- a/drivers/nvme/host/core.c ++++ b/drivers/nvme/host/core.c +@@ -4835,6 +4835,8 @@ static void nvme_fw_act_work(struct work_struct *work) + struct nvme_ctrl, fw_act_work); + unsigned long fw_act_timeout; + ++ nvme_auth_stop(ctrl); ++ + if (ctrl->mtfa) + fw_act_timeout = jiffies + + msecs_to_jiffies(ctrl->mtfa * 100); +@@ -4890,7 +4892,6 @@ static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result) + * firmware activation. + */ + if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) { +- nvme_auth_stop(ctrl); + requeue = false; + queue_work(nvme_wq, &ctrl->fw_act_work); + } +-- +2.43.0 + diff --git a/queue-6.1/series b/queue-6.1/series index e67e4f00477..a9d5086cf19 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -44,3 +44,10 @@ i2c-aspeed-handle-the-coalesced-stop-conditions-with.patch x86-xen-add-cpu-dependencies-for-32-bit-build.patch pinctrl-at91-pio4-use-dedicated-lock-class-for-irq.patch gpiolib-cdev-add-gpio_device-locking-wrapper-around-.patch +nvme-pci-fix-sleeping-function-called-from-interrupt.patch +drm-i915-mtl-limit-second-scaler-vertical-scaling-in.patch +drm-i915-relocate-intel_atomic_setup_scalers.patch +drm-i915-fix-intel_atomic_setup_scalers-plane_state-.patch +drm-i915-dpt-only-do-the-pot-stride-remap-when-using.patch +drm-i915-mtl-add-mtl-for-remapping-ccs-fbs.patch +drm-i915-fix-adl-tiled-plane-stride-when-the-pot-str.patch