From: Julian Seward <jseward@acm.org>
Date: Fri, 20 Aug 2004 23:39:55 +0000 (+0000)
Subject: Add (unused) pattern for generating rotate insns, as an example.
X-Git-Tag: svn/VALGRIND_3_0_1^2~1144
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5156544db332717a4247c3a1a7c3225abfce50d2;p=thirdparty%2Fvalgrind.git

Add (unused) pattern for generating rotate insns, as an example.


git-svn-id: svn://svn.valgrind.org/vex/trunk@190
---

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 5902f73bc6..9cf821ae8c 100644
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -294,6 +294,22 @@ static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
       X86AluOp   aluOp;
       X86ShiftOp shOp;
 
+#if 0
+      { DECLARE_PATTERN(p_rol32);
+        DEFINE_PATTERN(p_rol32,
+           binop(Iop_Or32,
+                 binop(Iop_Shl32,bind(0),bind(1)),
+                 binop(Iop_Shr32,
+                       bind(2),
+                       binop(Iop_Sub8,IRConst_U8(32),bind(3)))));
+        if (matchIRExpr(&mi,p_rol32,e)
+            && eqIRExpr(mi.bindee[0], mi.bindee[2])
+            && eqIRExpr(mi.bindee[1], mi.bindee[3])) {
+           /* emit roll */
+        }
+      }
+#endif
+
       /* Is it an addition or logical style op? */
       switch (e->Iex.Binop.op) {
          case Iop_Add8: case Iop_Add16: case Iop_Add32: