From: Jamin Lin Date: Tue, 3 Feb 2026 02:08:47 +0000 (+0800) Subject: hw/arm/aspeed_ast27x0: Sort SSP and TSP memmap tables by address X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=52591091647a4b48d9f5d1c9c3abe92f2f014908;p=thirdparty%2Fqemu.git hw/arm/aspeed_ast27x0: Sort SSP and TSP memmap tables by address Sort the SSP and TSP memmap tables to improve readability and make the definitions easier to maintain. No functional change. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20260203020855.1642884-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index cee937b37e..e4bcf0fa2a 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = { [ASPEED_DEV_SRAM] = 0x70000000, [ASPEED_DEV_INTC] = 0x72100000, [ASPEED_DEV_SCU] = 0x72C02000, + [ASPEED_DEV_TIMER1] = 0x72C10000, + [ASPEED_DEV_UART4] = 0x72C1A000, + [ASPEED_DEV_IPC0] = 0x72C1C000, [ASPEED_DEV_SCUIO] = 0x74C02000, + [ASPEED_DEV_INTCIO] = 0x74C18000, [ASPEED_DEV_UART0] = 0x74C33000, [ASPEED_DEV_UART1] = 0x74C33100, [ASPEED_DEV_UART2] = 0x74C33200, [ASPEED_DEV_UART3] = 0x74C33300, - [ASPEED_DEV_UART4] = 0x72C1A000, - [ASPEED_DEV_INTCIO] = 0x74C18000, - [ASPEED_DEV_IPC0] = 0x72C1C000, - [ASPEED_DEV_IPC1] = 0x74C39000, [ASPEED_DEV_UART5] = 0x74C33400, [ASPEED_DEV_UART6] = 0x74C33500, [ASPEED_DEV_UART7] = 0x74C33600, @@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = { [ASPEED_DEV_UART10] = 0x74C33900, [ASPEED_DEV_UART11] = 0x74C33A00, [ASPEED_DEV_UART12] = 0x74C33B00, - [ASPEED_DEV_TIMER1] = 0x72C10000, + [ASPEED_DEV_IPC1] = 0x74C39000, }; static const int aspeed_soc_ast27x0ssp_irqmap[] = { diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 9c11c016ca..68683a15d8 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = { [ASPEED_DEV_SRAM] = 0x70000000, [ASPEED_DEV_INTC] = 0x72100000, [ASPEED_DEV_SCU] = 0x72C02000, + [ASPEED_DEV_TIMER1] = 0x72C10000, + [ASPEED_DEV_UART4] = 0x72C1A000, + [ASPEED_DEV_IPC0] = 0x72C1C000, [ASPEED_DEV_SCUIO] = 0x74C02000, + [ASPEED_DEV_INTCIO] = 0x74C18000, [ASPEED_DEV_UART0] = 0x74C33000, [ASPEED_DEV_UART1] = 0x74C33100, [ASPEED_DEV_UART2] = 0x74C33200, [ASPEED_DEV_UART3] = 0x74C33300, - [ASPEED_DEV_UART4] = 0x72C1A000, - [ASPEED_DEV_INTCIO] = 0x74C18000, - [ASPEED_DEV_IPC0] = 0x72C1C000, - [ASPEED_DEV_IPC1] = 0x74C39000, [ASPEED_DEV_UART5] = 0x74C33400, [ASPEED_DEV_UART6] = 0x74C33500, [ASPEED_DEV_UART7] = 0x74C33600, @@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = { [ASPEED_DEV_UART10] = 0x74C33900, [ASPEED_DEV_UART11] = 0x74C33A00, [ASPEED_DEV_UART12] = 0x74C33B00, - [ASPEED_DEV_TIMER1] = 0x72C10000, + [ASPEED_DEV_IPC1] = 0x74C39000, }; static const int aspeed_soc_ast27x0tsp_irqmap[] = {