From: James Clark Date: Mon, 9 Jun 2025 10:19:05 +0000 (+0100) Subject: coresight: trbe: Add ISB after TRBLIMITR write X-Git-Tag: v6.18-rc1~74^2~5^2~26 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=52c0164b2526bce7013fca193e076f6d9eec9c95;p=thirdparty%2Flinux.git coresight: trbe: Add ISB after TRBLIMITR write DEN0154 states that hardware will be allowed to ignore writes to TRB* registers while the trace buffer is enabled. Add an ISB to ensure that it's disabled before clearing the other registers. This is purely defensive because it's expected that arm_trbe_disable() would be called before teardown which has the required ISB. Fixes: a2b579c41fe9 ("coresight: trbe: Remove redundant disable call") Signed-off-by: James Clark Reviewed-by: Yeoreum Yun Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250609-james-cs-trblimitr-isb-v1-1-3a2aa4ee6770@linaro.org --- diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 8267dd1a2130d..10f3fb401edf6 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -257,6 +257,7 @@ static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata) static void trbe_reset_local(struct trbe_cpudata *cpudata) { write_sysreg_s(0, SYS_TRBLIMITR_EL1); + isb(); trbe_drain_buffer(); write_sysreg_s(0, SYS_TRBPTR_EL1); write_sysreg_s(0, SYS_TRBBASER_EL1);