From: Jonas Jelonek <jelonek.jonas@gmail.com>
Date: Mon, 15 Dec 2025 18:45:54 +0000 (+0000)
Subject: realtek: pcs: rtl931x: reorder modes in mode configuration
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5334b41b00051912cbc7a1bf23eb681e467ac804;p=thirdparty%2Fopenwrt.git

realtek: pcs: rtl931x: reorder modes in mode configuration

Reorder the modes within the switch statement in
rtpcs_931x_sds_config_mode to have a proper and non-confusing order.
Have fiber modes first and MII modes after, and sort all modes in
ascending speed/capabilities order.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21184
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---

diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
index 1ed8858ff18..347800de784 100644
--- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
@@ -2685,8 +2685,43 @@ static int rtpcs_931x_sds_config_mode(struct rtpcs_serdes *sds,
 	case RTPCS_SDS_MODE_OFF:
 		break;
 
-	case RTPCS_SDS_MODE_XSGMII:
+	case RTPCS_SDS_MODE_1000BASEX:
+		rtpcs_sds_write_bits(sds, 0x43, 0x13, 15, 14, 0);
+
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 12, 12, 1);
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 6, 6, 1);
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 13, 13, 0);
+		break;
+
+	case RTPCS_SDS_MODE_2500BASEX:
+		rtpcs_sds_write_bits(sds, 0x41, 0x14, 8, 8, 1);
+		break;
+
+	case RTPCS_SDS_MODE_10GBASER: /* 10GR1000BX_AUTO */
+		/* configure 10GR fiber mode=1 */
+		rtpcs_sds_write_bits(sds, 0x1f, 0xb, 1, 1, 1);
+
+		/* init fiber_1g */
+		rtpcs_sds_write_bits(sds, 0x43, 0x13, 15, 14, 0);
 
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 12, 12, 1);
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 6, 6, 1);
+		rtpcs_sds_write_bits(sds, 0x42, 0x0, 13, 13, 0);
+
+		/* init auto */
+		rtpcs_sds_write_bits(sds, 0x1f, 13, 15, 0, 0x109e);
+		rtpcs_sds_write_bits(sds, 0x1f, 0x6, 14, 10, 0x8);
+		rtpcs_sds_write_bits(sds, 0x1f, 0x7, 10, 4, 0x7f);
+		break;
+
+	case RTPCS_SDS_MODE_SGMII:
+		rtpcs_sds_write_bits(sds, 0x24, 0x9, 15, 15, 0);
+
+		/* this was in rtl931x_phylink_mac_config in dsa/rtl83xx/dsa.c before */
+		rtpcs_931x_sds_cmu_band_set(sds, true, 62, PHY_INTERFACE_MODE_SGMII);
+		break;
+
+	case RTPCS_SDS_MODE_XSGMII:
 		if (chiptype) {
 			/* fifo inv clk */
 			rtpcs_sds_write_bits(sds, 0x41, 0x1, 7, 4, 0xf);
@@ -2747,42 +2782,6 @@ static int rtpcs_931x_sds_config_mode(struct rtpcs_serdes *sds,
 		}
 		break;
 
-	case RTPCS_SDS_MODE_10GBASER: /* 10GR1000BX_AUTO */
-		/* configure 10GR fiber mode=1 */
-		rtpcs_sds_write_bits(sds, 0x1f, 0xb, 1, 1, 1);
-
-		/* init fiber_1g */
-		rtpcs_sds_write_bits(sds, 0x43, 0x13, 15, 14, 0);
-
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 12, 12, 1);
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 6, 6, 1);
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 13, 13, 0);
-
-		/* init auto */
-		rtpcs_sds_write_bits(sds, 0x1f, 13, 15, 0, 0x109e);
-		rtpcs_sds_write_bits(sds, 0x1f, 0x6, 14, 10, 0x8);
-		rtpcs_sds_write_bits(sds, 0x1f, 0x7, 10, 4, 0x7f);
-		break;
-
-	case RTPCS_SDS_MODE_1000BASEX:
-		rtpcs_sds_write_bits(sds, 0x43, 0x13, 15, 14, 0);
-
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 12, 12, 1);
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 6, 6, 1);
-		rtpcs_sds_write_bits(sds, 0x42, 0x0, 13, 13, 0);
-		break;
-
-	case RTPCS_SDS_MODE_SGMII:
-		rtpcs_sds_write_bits(sds, 0x24, 0x9, 15, 15, 0);
-
-		/* this was in rtl931x_phylink_mac_config in dsa/rtl83xx/dsa.c before */
-		rtpcs_931x_sds_cmu_band_set(sds, true, 62, PHY_INTERFACE_MODE_SGMII);
-		break;
-
-	case RTPCS_SDS_MODE_2500BASEX:
-		rtpcs_sds_write_bits(sds, 0x41, 0x14, 8, 8, 1);
-		break;
-
 	case RTPCS_SDS_MODE_QSGMII:
 	default:
 		return -ENOTSUPP;