From: Florian Krohm <florian@eich-krohm.de>
Date: Sat, 3 Aug 2013 19:36:55 +0000 (+0000)
Subject: Rename ppc_cache_line_szB to indicate that this is the size
X-Git-Tag: svn/VALGRIND_3_9_0^2~60
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5422872a9185564472ce982a6c53018e9f080db2;p=thirdparty%2Fvalgrind.git

Rename ppc_cache_line_szB to indicate that this is the size
of the instruction cache.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2735
---

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index f420bb5acf..fd9ac5b84f 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -6654,7 +6654,7 @@ static Bool dis_cache_manage ( UInt         theInstr,
    UChar rB_addr = ifieldRegB(theInstr);
    UInt  opc2    = ifieldOPClo10(theInstr);
    UChar b0      = ifieldBIT0(theInstr);
-   UInt  lineszB = guest_archinfo->ppc_cache_line_szB;
+   UInt  lineszB = guest_archinfo->ppc_icache_line_szB;
    Bool  is_dcbzl = False;
 
    IRType ty     = mode64 ? Ity_I64 : Ity_I32;
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index 05ca8fa706..6297a5de98 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1171,10 +1171,10 @@ const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps )
 /* Write default settings info *vai. */
 void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai )
 {
-   vai->hwcaps             = 0;
-   vai->ppc_cache_line_szB = 0;
-   vai->ppc_dcbz_szB       = 0;
-   vai->ppc_dcbzl_szB      = 0;
+   vai->hwcaps              = 0;
+   vai->ppc_icache_line_szB = 0;
+   vai->ppc_dcbz_szB        = 0;
+   vai->ppc_dcbzl_szB       = 0;
 
    vai->hwcache_info.num_levels = 0;
    vai->hwcache_info.num_caches = 0;
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index f29e41c1c9..3830b710bd 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -245,8 +245,8 @@ typedef
       /* The following two fields are mandatory. */
       UInt hwcaps;
       VexCacheInfo hwcache_info;
-      /* PPC32/PPC64 only: size of cache line */
-      Int ppc_cache_line_szB;
+      /* PPC32/PPC64 only: size of instruction cache line */
+      Int ppc_icache_line_szB;
       /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions
        * (bug#135264) */
       UInt ppc_dcbz_szB;
diff --git a/VEX/switchback/switchback.c b/VEX/switchback/switchback.c
index 990c7d3e08..ce577fa39e 100644
--- a/VEX/switchback/switchback.c
+++ b/VEX/switchback/switchback.c
@@ -846,7 +846,7 @@ void make_translation ( Addr64 guest_addr, Bool verbose )
 
    LibVEX_default_VexArchInfo(&vex_archinfo);
    vex_archinfo.subarch = VexSubArch;
-   vex_archinfo.ppc_cache_line_szB = CacheLineSize;
+   vex_archinfo.ppc_icache_line_szB = CacheLineSize;
 
    /* */
    vta.arch_guest       = VexArch;
diff --git a/VEX/test_main.c b/VEX/test_main.c
index 58929817f7..5ddd5f4268 100644
--- a/VEX/test_main.c
+++ b/VEX/test_main.c
@@ -178,7 +178,7 @@ int main ( int argc, char** argv )
 
       LibVEX_default_VexArchInfo(&vai_ppc32);
       vai_ppc32.hwcaps = 0;
-      vai_ppc32.ppc_cache_line_szB = 128;
+      vai_ppc32.ppc_icache_line_szB = 128;
 
       LibVEX_default_VexArchInfo(&vai_arm);
       vai_arm.hwcaps = VEX_HWCAPS_ARM_VFP3 | VEX_HWCAPS_ARM_NEON | 7;