From: Pan Li <pan2.li@intel.com>
Date: Sun, 19 Jul 2026 09:55:49 +0000 (+0800)
Subject: RISC-V: Adjust test case due to allow vwcvt.f.f.v overlap
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5453f858146e60204fa3cc0fd01d9ab38ea837cc;p=thirdparty%2Fgcc.git

RISC-V: Adjust test case due to allow vwcvt.f.f.v overlap

Remove the xfail due to overlap changes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-7.c: Remove xfail.
	* gcc.target/riscv/rvv/base/pr112431-8.c: Ditto.
	* gcc.target/riscv/rvv/base/pr112431-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
index 59cbd7ff4be..b52c0c3f8d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
@@ -101,4 +101,4 @@ foo (char const *buf, size_t len)
 /* { dg-final { scan-assembler-not {vmv2r} } } */
 /* { dg-final { scan-assembler-not {vmv4r} } } */
 /* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
index 3a8ca02bd21..ab56d0d69af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
 /* { dg-final { scan-assembler-not {vmv2r} } } */
 /* { dg-final { scan-assembler-not {vmv4r} } } */
 /* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
index 88ab1d9da5c..82f369c0cd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
 /* { dg-final { scan-assembler-not {vmv2r} } } */
 /* { dg-final { scan-assembler-not {vmv4r} } } */
 /* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */